Note (1): Value depends on the current state of the LX4/CX4 select LX4_MODE pin. Although IEEE 802.3ae specifies R/W bits, only valid values ma" />
參數(shù)資料
型號: ISL35822LPIK
廠商: Intersil
文件頁數(shù): 15/75頁
文件大?。?/td> 0K
描述: IC CLOCK/DATA RECOVERY 192EBGA-B
標(biāo)準(zhǔn)包裝: 90
類型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
輸入: CML
輸出: CML,CMOS
電路數(shù): 1
比率 - 輸入:輸出: 8:8
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.59Gbps
電源電壓: 1.3 V ~ 1.41 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 192-EBGA
供應(yīng)商設(shè)備封裝: 192-EBGA-B(17x17)
包裝: 托盤
22
Note (1): Value depends on the current state of the LX4/CX4 select LX4_MODE pin. Although IEEE 802.3ae specifies R/W bits, only valid values may be written; since
the pin controls the available valid value, no meaningful write is possible.
Table 8. IEEE DEVICES IN PACKAGE REGISTERS
MDIO REGISTER ADDRESSES = 1.5, 3.5, 4.5 ([1,3:4].0005’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
[1,3:4].5.15:8
Reserved
000’h
[1,3,4].5.7
Link Partner
Link Partner PMA/PMD present 0’b
RO
Device has no Link Partner
[1,3,4].5.6
10PASS-TS tone table
10PASS-TS tone table present 0’b
RO
Device has no 10PASS-TS tone table
[1,3:4].5.5
DTE XS
DTE XS Present
0’b
RO
Device ignores DEVAD 5
[1,3:4].5.4
PHY XS
PHY XS Present
1’b
RO
Device responds to DEVAD 4
[1,3:4].5.3
PCS
PCS Present
1’b
RO
Device responds to DEVAD 3
[1,3:4].5.2
WIS
WIS Present
0’b
RO
Device ignores DEVAD 2
[1,3:4].5.1
PMD_PMA
PMD/PMA Present
1’b
RO
Device responds to DEVAD 1
[1,3:4].5.0
Cls_22
Clause 22 registers
0’b
RO
Device ignores Clause 22
MDIO REGISTER ADDRESSES = 1.6, 3.6, 4.6 ([1,3:4].0006’h)
[1,3:4].6.15
VndrDEV2
Vendor Specific DEV2
0’b
RO
Device ignores DEVAD 31
[1,3:4].6.14
VndrDEV1
Vendor Specific DEV1
0’b
RO
Device ignores DEVAD 30
[1,3,4].6.13
Clause 22 extn.
Clause 22 extension
0’b
RO
Device has no Clause 22 extension
[1,3:4].6.12:0
Reserved
000’h
Table 9. IEEE PMA/PMD TYPE SELECT REGISTER
MDIO REGISTER ADDRESSES = 1.7 (1.0007’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.7.15:4
Reserved
000’h
1.7.3:0
PMA/PMD Type
0100 = 10GBASE-LX4
0000 = 10GBASE-CX4
P’b(1)
RO
LX4_MODE select pin high is LX4 value,
low is CX4 value
Table 10. IEEE PMA/PMD STATUS 2 DEVICE PRESENT & FAULT SUMMARY REGISTER
MDIO REGISTER ADDRESSES = 1.8 (1.0008’h)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
1.8.15:14
Device present
10 = Device present
10’b
RO
When read as “10”, it indicates that a device is
present at this device address
1.8.13
TXLocalFlt Ability
1 = PMA/PMD can detect TX
Fault
1’b
RO
PMA/PMD has the ability to detect a Local Fault
on Transmit Path
1.8.12
RXLocalFlt Ability
1 = PMA/PMD can detect RX
Fault
1’b
RO
PMA/PMD has the ability to detect a Local Fault
on Receive Path
1.8.11
TXLocalFlt
1 = TX Local Fault; on Egress
channel
0’b
RO LH(1)
PLL lock fail (missing REFCLK) or TX_FAULT pin
active
1.8.10
RXLocalFlt
1 = RX Local Fault; on Ingress
channel
0’b
RO
LH(1,2)
PLL lock fail (missing REFCLK), or Loss of Signal
in 1.10 (1.000A’h)
1.8.9
Ext Ability
1 = Extended Ability Register
present.
1’b
RO
Device has Extended Ability Register in 1.11
(1.000B’h)
1.8.8
TX Disable
1 = Can Disable TX
1’b
RO
Device can Disable Transmitter
1.8.7
10GBASE-SR
0 = cannot perform
0’b
RO
Device cannot be 10GBASE-SR
1.8.6
10GBASE-LR
0 = cannot perform
0’b
RO
Device cannot be 10GBASE-LR
ISL35822
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