參數資料
型號: IS66WVD409616ALL-7010BLI
元件分類: SRAM
英文描述: 4M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封裝: 8 X 6 MM, MO-207, VFBGA-54
文件頁數: 27/52頁
文件大?。?/td> 1128K
代理商: IS66WVD409616ALL-7010BLI
IS66WVD409616ALL
Advanced Information
33
Rev.00A | January 2010
www.issi.com - SRAM@issi.com
Table18 . Burst WRITE Cycle Timing Requirements
Symbol
Parameter
-7013
-7010
-7008
Unit
Note
Min
Max
Min
Max
Min
Max
tAS
Address and ADV# LOW Setup
Time
0
ns
1
tCBPH
CE# High between Subsequent
Burst or Mixed-Mode Operations
5
6
ns
2
tCEM
Maximum CE# Pulse width
4
us
2
tCLK
CLK Period
7.5
9.62
12.5
ns
tCSP
CE# Setup Time to Active CLK
Edge
2.5
3
4
ns
tHD
Hold Time from Active CLK Edge
2
ns
tKH/tKL
CLK HIGH or LOW Time
3
4
ns
tKW
CLK to WAIT Valid
5.5
7
9
ns
3
tSP
Setup time to Active CLK Edge
2
3
ns
tT
CLK Rise or Fall Time
1.2
1.6
1.8
ns
tWZ
CE# high to WAIT High-Z
7
ns
4
Notes:
1. tAS required if tCSP > 20ns.
2. A refresh opportunity must be provided every tCEM by taking CE# HIGH.
3. tKW value for -7013 is for variable LC = 4 and fixed LC = 8 only. For other LC settings, this
parameter will be 7ns for -7013 devices.
4. Low-Z to High-Z timings are tested with the circuit shown in Figure 16.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
Symbol
Parameter
-70
Unit
Notes
Min
Max
tDPD
Time from DPD entry to DPD exit
150
us
tDPDX
CE# LOW time to exit DPD
70
ns
tPU
Initialization Period (required before normal operations)
150
us
Table19 . Initialization and DPD Timing Requirements
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