參數(shù)資料
型號: IS66WVD409616ALL-7010BLI
元件分類: SRAM
英文描述: 4M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封裝: 8 X 6 MM, MO-207, VFBGA-54
文件頁數(shù): 22/52頁
文件大?。?/td> 1128K
代理商: IS66WVD409616ALL-7010BLI
IS66WVD409616ALL
Advanced Information
29
Rev.00A | January 2010
www.issi.com - SRAM@issi.com
Notes:
1. Input signals may overshoot to VDDQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to Vss – 1.0V for periods less than 2ns during transitions.
3. BCR[5:4] = 01b (default setting of one-half drive strength).
4. This parameter is specified with the outputs disabled to avoid external loading effects.
User must add required current to drive output capacitance expected in the actual system.
5. ISB (MAX) values measured with PAR set to FULL ARRAY at +85°C. In order to achieve low
standby current, all inputs must be driven to either VDDQ or VSS. ISB might be set slightly
higher for up to 500ms after power-up, or when entering standby mode.
Description
Conditions
Symbol
TYP
MAX
Unit
Deep Power-Down
VIN=VDDQ or 0V
VDD,VDDQ=1.95V, +85°C
IDPD
3
10
uA
Table 13. Deep Power-Down Specifications
Description
Conditions
Symbol
MIN
MAX
Unit
Note
Input Capacitance
TC=+25°C;
f=1Mhz;
VIN=0V
CIN
2.0
6.0
pF
1
Input/Output Capacitance (ADQ)
CIO
3.0
6.5
pF
1
Table 14. Capacitance
Notes:
Typical (TYP) IDPD value applies across all operating temperatures and voltages.
Notes:
1. These parameters are verified in device characterization and are not 100% tested.
VDDQ/23 Output
Figure 15. AC Input/Output Reference Waveform
Test Points
∫∫
VDDQ/22 Output
VDDQ
VSS
Notes:
1. AC test inputs are driven at VDDQ for a logic 1 and VSS for a logic 0. Input rise and fall times
(10% to 90%) < 1.6ns.
2. Input timing begins at VDDQ/2.
3. Output timing ends at VDDQ/2.
DUT
30pF
50
VDDQ/2
Test Point
Figure 16. Output Load Circuit
Notes:
All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).
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