參數(shù)資料
型號(hào)： IS66WVD409616ALL-7010BLI
元件分類： SRAM
英文描述： 4M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封裝： 8 X 6 MM, MO-207, VFBGA-54
文件頁數(shù)： 25/52頁
文件大?。?/td> 1128K
代理商： IS66WVD409616ALL-7010BLI
IS66WVD409616ALL
Advanced Information
31
Rev.00A | January 2010
www.issi.com - SRAM@issi.com
Table16 . Burst READ Cycle Timing Requirements
Symbol
Parameter
-7013
-7010
-7008
Unit
Note
Min
Max
Min
Max
Min
Max
tAA
Address Acess Time (Fixed Latency)
70
ns
tAADV
ADV# Access Time (Fixed Latency)
70
ns
tABA
Burst to READ Access Time
(Variable Latency)
35.5
35.9
46.5
ns
tACLK
CLK to Output Delay
5.5
7
9
ns
1
tCBPH
CE# High between Subsequent
Burst or Mixed-Mode Operations
5
6
ns
2
tCEM
Maximum CE# Pulse width
4
us
2
tCLK
CLK Period
7.5
9.62
12.5
ns
tCO
Chip Select Access Time (Fixed
Latency)
70
ns
tCSP
CE# Setup Time to Active CLK Edge
2.5
3
4
ns
tHD
Hold Time from Active CLK Edge
2
ns
tHZ
Chip Disable to High-Z Output
7
ns
3
tKH/tKL
CLK HIGH or LOW Time
3
4
ns
tKOH
Output Hold from CLK
2
ns
tKW
CLK to WAIT Valid
5.5
7
9
ns
1
tOE
Burst OE# LOW to Output Valid
20
ns
tOHZ
OE# high to High-Z Output
7
ns
4
tOLZ
OE# low to Low-Z output
3
ns
4
tSP
Setup time to Active CLK Edge
2
3
ns
tT
CLK Rise or Fall Time
1.2
1.6
1.8
ns
tWZ
CE# high to WAIT High-Z
7
ns
3
Notes:
1. tACLK and tKW values for -7013 are for variable LC = 4 and fixed LC = 8 only. For other LC
settings, these parameters will be 7ns for -7013 devices.
2. A refresh opportunity must be provided every tCEM by taking CE# HIGH.
3. Low-Z to High-Z timings are tested with the circuit shown in Figure 16.
The High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
4. High-Z to Low-Z timings are tested with the circuit shown in Figure 16.
The Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
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