參數(shù)資料
型號(hào): IS43R32800B-5BL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 8M X 32 DDR DRAM, 0.7 ns, PBGA144
封裝: 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-144
文件頁(yè)數(shù): 34/39頁(yè)
文件大?。?/td> 507K
代理商: IS43R32800B-5BL
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08
IS43R32800B
CL K, /CLK
Input
Cl ock: CL Ka nd/CLK aredifferentialclock inputs.A ll addressand control
inputsignals aresampled on thecrossingofthe positive edge of CL Ka nd
negative edgeof /CLK .Output(read)dataisreferencedtothe crossingsof
CL Ka nd /CLK (bothdirections of crossing).
CK EI nput
Cl ockE nable: CK Econtrolsinternalclock.W henCKE is low, internal clock
forthe followingcycle is ceased.C KE is also used to select auto/selfrefresh.
Af terselfrefresh mode is started, CK Ebecomes asynchronous input. Self refresh
is maintained as long as CK Ei slow.
/CSI nput
Chip Select:W hen/CS is high,any commandmeans No Operation.
/RAS ,/CAS, /WEI nput
Combinationof/RA S, /CAS ,/WE definesbasic commands.
A0-1 1Input
A0-1 1specify theRow /ColumnAddress in conjunctionwithBA0,1.T he
RowAddressisspecifi ed by A0-11. TheColumnAddress is specified by
A0-7 ,A 9. A8 is also used to indicate precharge option.WhenA8is
high at aread/ writecommand,anautoprecharge is performed. When A8
is high at aprecharge command, allbanks areprecharged.
BA 0,1
Input
DQ0-31
Input/Output
DQS0- 3
VDD, Vs s
PowerSupply
PowerSupply forthe memory arrayand peripheral circuitry.
VDDQ ,VssQ
PowerSupply
VDDQ andVssQ are suppliedtothe Output Buffersonly.
Bank Address: BA 0,1specifies oneoffourbanks to whicha command is
applied. BA 0,1mustbeset with ACT, PR E, READ, WR IT Ecommands.
Data Input/Output:D atabus
Data Strobe:Outputwith read data,inputwith write data.E dge-aligned
with read data,centeredinwrite data.Usedtocapture writedata.
DQS 0for DQ0- DQ7, DQS 1for DQ8- DQ15, DQS2 forDQ16- DQ23,
DQS3 for DQ24- DQ31.
SYMBOL
TYPE
DESCRIPTION
DM0- 3
Input
InputDataMask: DM is an inputmask signal forwrite data.I nput data
is masked when DM is sampledHIG Halong with that inputdata
duringa WR IT Eaccess. DM is sampledon bothedgesofD QS.
Al though DM pins areinput only,the DM loadingmatches theDQ
andDQS loading. DM 0for DQ0 - DQ7,DM1 for DQ8 - DQ15,
DM 2for DQ16- DQ23, DM 3for DQ24- DQ31.
Input/ Output
Vref
Input
SST L_ 2reference voltage.
PIN FUNCTIONS
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