參數(shù)資料
型號(hào): IS43R32800B-5BL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 8M X 32 DDR DRAM, 0.7 ns, PBGA144
封裝: 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-144
文件頁(yè)數(shù): 11/39頁(yè)
文件大?。?/td> 507K
代理商: IS43R32800B-5BL
Integrated Silicon Solution, Inc. — www.issi.com
19
Rev. 00D
03/19/08
IS43R32800B
/CS
/RAS
/CAS
/WE
A11-A0
/CLK
V
CL K
BA 0
BA 1
R: Reserved forFutureUse
0NO
1Y ES
DL LR eset
0Sequential
1Interleaved
BurstType
BT =0
BT =1
00 0R
R
00 12
2
01 04
4
01 18
8
10 0R
R
10 1R
R
11 0R
R
11 1R
R
BL
Burst
Length
/CAS La tency
00 0R
00 1R
01 02
01 13
10 0R
10 1R
11 02.5
11 1R
CL
Latency
Mode
BA 1B A0 A11A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
00
0DR0
BT
LT MO DE
BL
MODE REGISTER DEFINITION
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure “MODE REGISTER
DEFINITION”. The Mode Register is programmed via the MODE REGISTER SET (MRS) command (with BA0 = 0 and
BA1 = 0) and will retain stored information until it is programmed again or the device loses power.
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify
the CAS latency, and A7-A11 specify the operating mode.
The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the
specified time before initiating any subsequent operation. After tMRD from a MRS command the DDR SDRAM is ready for
a new command. Violating either of these requirements will result in unspecified operation.
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