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參數(shù)資料
| 型號： | INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486山西處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 23/38頁 |
| 文件大?。?/td> | 346K |
| 代理商： | INTEL486 SX |
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Embedded Ultra-Low Power Intel486 SX Processor
19
4.4
Low-Power Features
As with other Intel486 processors, the embedded
ULP Intel486 SX processor minimizes power
consumption by providing the Auto HALT Power
Down, Stop Grant, and Stop Clock states (see
Figure 4). The embedded ULP Intel486 SX
processor has an Auto Clock Freeze feature that
further conserves power by judiciously deactivating
its internal clocks while in the Normal Execution
Mode.
The
power-conserving
designed such that it does not degrade processor
performance or require changes to AC timing specifi-
cations.
mechanism
is
4.4.1
Auto Clock Freeze
To reduce power consumption, during the following
bus cycles — under certain conditions — the
processor slows-up or freezes some internal clocks:
Data-Read Wait Cycles (Memory, I/O and Interrupt
Acknowledge)
Data-Write Wait Cycles (Memory, I/O)
HOLD/HLDA Cycles
AHOLD Cycles
BOFF Cycles
Power is conserved during the wait periods in these
cycles until the appropriate external-system signals
are sent to the processor. These signals include:
READY
NMI, SMI#, INTR, and RESET
BOFF#
FLUSH#
EADS#
BS8#, BS16# and KEN# transitions
The embedded ULP Intel486 SX processor also
reduces power consumption by temporarily freezing
the clocks of its internal logic blocks. When a logic
block is idle or in a wait state, its clock is frozen.
4.5
CPUID Instruction
The embedded ULP Intel486 SX processor supports
the CPUID instruction (see Table 9). Because not all
Intel processors support the CPUID instruction, a
simple test can determine if the instruction is
supported. The test involves the processor’s ID Flag,
which is bit 21 of the EFLAGS register. If software
can change the value of this flag, the CPUID
instruction is available. The actual state of the ID
Flag bit is irrelevant and provides no significance to
the hardware. This bit is cleared (reset to zero) upon
device reset (RESET or SRESET) for compatibility
with Intel486 processor designs that do not support
the CPUID instruction.
CPUID-instruction details are provided here for the
embedded ULP Intel486 SX processor. Refer to Intel
Application Note AP-485
Intel Processor Identifi-
cation with the CPUID Instruction
(Order No.
241618) for a description that covers all aspects of
the CPUID instruction and how it pertains to other
Intel processors.
4.5.1
Operation of the CPUID Instruction
The CPUID instruction requires the software
developer to pass an input parameter to the
processor in the EAX register. The processor
response is returned in registers EAX, EBX, EDX,
and ECX.
Table 9. CPUID Instruction Description
OP CODE
Instruction
Processor
Core Clocks
Parameter passed in
EAX
(Input Value)
Description
0F A2
CPUID
9
0
Vendor (Intel) ID String
14
1
Processor Identification
9
> 1
Undefined (Do Not Use)
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