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參數(shù)資料
| 型號(hào)： | INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486山西處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 19/38頁 |
| 文件大小： | 346K |
| 代理商： | INTEL486 SX |
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Embedded Ultra-Low Power Intel486 SX Processor
15
4.0
ARCHITECTURAL AND
FUNCTIONAL OVERVIEW
The embedded ULP Intel486 SX processor archi-
tecture is essentially the same as the 3.3 V Intel486
SX processor with a 1X clock (CLK) input. Refer to
the
Embedded
Intel486
Developer’s Manual, order number 273032, for a
description of the ULP Intel486 SX processor. The
following notes supplement the information in the
manual.
The information pertaining to parity signals for the
external data bus does not apply. The embedded
ULP Intel486 SX processor does not have DP0#,
DP1#, DP2#, DP3# and PCHK# signal pins.
References to the Upgrade Power Down Mode do
not apply. The embedded ULP Intel486 SX
processor does not have the UP# signal pin and
does not support the Intel OverDrive
processor.
References to “V
” are called “V
” by the
embedded ULP Intel486 SX processor when the
supply voltage pertains to the processor’s external
interface drivers and receivers. The term “V
”
pertains only to the processor core supply voltage
of the embedded ULP Intel486 SX processor.
Information about the split-supply voltage is
provided in this datasheet.
The Phase-Locked Loop (PLL) of the 1X clock
(CLK) input has been replaced by a proprietary
Differential Delay Line (DDL) that has a faster
startup and recovery time. Datasheet references to
the PLL and its 1 ms recovery time are replaced
with the DDL circuit and its eight-CLK recovery
time. Information about the DDL and startup and
recovery latency is provided in this datasheet.
The embedded ULP Intel486 SX processor has
level-keeper circuits for its external 32-bit data bus
signals (D31-D0). The Intel486 SX processor
floats its data bus instead. More information about
the level-keeper circuitry is provided in this
datasheet.
The datasheet describes the processor supply-
current consumption for the Auto HALT Power
Down, Stop Grant, and Stop Clock states. This
supply-current consumption for the embedded
ULP Intel486 SX processor is much less than that
of the Intel486 SX processor. Information about
power consumption and these states is provided in
this datasheet.
The CPU ID, Boundary-Scan (JTAG) ID, and
boundary-scan register bits for the embedded ULP
Intel486 SX processor are in this datasheet.
Processor
Family
The embedded ULP Intel486 SX processor has
one pin reserved for possible future use. This pin
is an input signal, pin 166. It is called
RESERVED# and must be connected to a 10-K
pull-up resistor.
4.1
Separate Supply Voltages
The embedded ULP Intel486 SX processor has
separate voltage-supply planes for its internal core-
processor circuits and its external driver/receiver
circuits. The supply voltage for the internal core
processor is named V
CC
and the supply voltage for
the external circuits is named V
CCP
.
For a single-supply voltage design, the embedded
ULP Intel486 SX processor is functional at
3.3 V ± 0.3 V. In this type of system design, the
processor’s V
CC
and V
CCP
pins must be tied to the
same power plane.
Even though V
CCP
must be 3.3 V ± 0.3 V, the
processor’s external-output circuits can drive TTL-
compatible components. However, the processor’s
external-input circuits do not allow connection to
TTL-compatible components. Section 5.2, DC Speci-
fications (pg. 22) contains the DC specifications for
the processor’s input and output signals.
For lower-power operation, a separate, lower voltage
for V
CC
can be chosen, but V
CCP
must be
3.3 V ± 0.3 V. Any voltage value between 2.4 V and
3.3 V can be chosen for V
CC
for guaranteed
processor operation up to 25 MHz. The embedded
ULP Intel486 SX processor can also operate at
33 MHz, provided the V
CC
value chosen is between
2.7 V and 3.3 V. Section 5.2, DC Specifications (pg.
22) defines supply voltage specifications.
In systems with separate V
CC
and V
CCP
power
planes, the processor-core voltage supply must
always be less than or equal to the processor’s
external-interface voltage supply; e.g., the system
design must guarantee:
V
CC
≤
V
CCP
Violating this relationship causes excessive power
consumption. Limited testing has shown no
component damage when this relationship is
violated. However, prolonged violation is not recom-
mended and component integrity is not guaranteed.
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