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參數(shù)資料
| 型號： | INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486山西處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 11/38頁 |
| 文件大?。?/td> | 346K |
| 代理商： | INTEL486 SX |
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Embedded Ultra-Low Power Intel486 SX Processor
7
3.2
Pin Quick Reference
The following is a brief pin description. For detailed signal descriptions refer to
Appendix A, “Signal Descrip-
tions,” in the Embedded Intel486 Processor Family Developer’s Manual,
order No. 273021.
Table 4. Embedded ULP Intel486
SX Processor Pin Descriptions
(Sheet 1 of 6)
Symbol
CLK
Type
I
Name and Function
Clock
provides the fundamental timing and internal operating frequency for the
embedded ULP Intel486 SX processor. All external timing parameters are
specified with respect to the rising edge of CLK.
ADDRESS BUS
A31-A4
A3–A2
I/O
O
Address Lines
A31–A2, together with the byte enable signals, BE3#–BE0#,
define the physical area of memory or input/output space accessed. Address lines
A31–A4 are used to drive addresses into the embedded ULP Intel486 SX
processor to perform cache line invalidation. Input signals must meet setup and
hold times t
22
and t
23
. A31–A2 are not driven during bus or address hold.
Byte Enable
signals indicate active bytes during read and write cycles. During the
first cycle of a cache fill, the external system should assume that all byte enables
are active. BE3#–BE0# are active LOW and are not driven during bus hold.
BE3# applies to D31–D24
BE2# applies to D23–D16
BE1# applies to D15–D8
BE0# applies to D7–D0
BE3#
BE2#
BE1#
BE0#
O
O
O
O
DATA BUS
D31
–D0
I/O
Data Lines.
D7–D0 define the least significant byte of the data bus; D31–D24
define the most significant byte of the data bus. These signals must meet setup
and hold times t
and t
for proper operation on reads. These pins are driven
during the second and subsequent clocks of write cycles.
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