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參數(shù)資料
| 型號： | INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486山西處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 22/38頁 |
| 文件大?。?/td> | 346K |
| 代理商： | INTEL486 SX |
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Embedded Ultra-Low Power Intel486 SX Processor
18
4.3
Level-Keeper Circuits
To obtain the lowest possible power consumption
during the Stop Grant and Stop Clock states, system
designers must ensure that:
input signals with pull-up resistors are not driven
LOW
input signals with pull-down resistors are not
driven HIGH
See Table 8, Input Pins (pg. 14) for the list of signals
with internal pull-up and pull-down resistors.
All other input pins except A31-A4 and D31-D0 must
be driven to the power supply rails to ensure lowest
possible current consumption.
During the Stop Grant and Stop Clock states, most
processor output signals maintain their previous
condition, which is the level they held when entering
the Stop Grant state. In response to HOLD driven
active during the Stop Grant state when the CLK
input is running, the embedded ULP Intel486 SX
processor generates HLDA and floats all output and
input/output signals which are floated during the
HOLD/HLDA state. When HOLD is deasserted,
processor signals which maintain their previous state
return to the state they were in prior to the
HOLD/HLDA sequence.
The data bus (D31-D0) also maintains its previous
state during the Stop Grant and Stop Clock states,
but does so differently, as described in the following
paragraphs.
The embedded ULP Intel486 SX processor’s data
bus pins (D31-D0) have level keepers which
maintain their previous states while in the Stop Grant
and Stop Clock states. In response to HOLD driven
active during the Stop Grant state when the CLK
input is running, the embedded ULP Intel486 SX
processor generates HLDA and floats D31-D0
throughout the HOLD/HLDA cycles. When HOLD is
deasserted, the processor’s D31-D0 signals return to
the states they were in prior to the HOLD/HLDA
sequence.
At all other times during the Stop Grant and Stop
Clock states, the processor maintains the logic
levels of D31-D0. When the external system circuitry
drives D31-D0 to different logic levels, the processor
flips its D31-D0 logic levels to match the ones driven
by the external system. The processor maintains
(keeps) these new levels even after the external
circuitry stops driving D31-D0.
For some system designs, external resistors may not
be required on D31- D0 (they are required on
previous Intel486 SX processor designs). System
designs that never request Bus Hold during the Stop
Grant and Stop Clock states might not require
external resistors. If the system design uses Bus
Hold during these states, the processor disables the
level-keepers and floats the data bus. This type of
design would require some kind of data bus termi-
nation to minimize power consumption. It is strongly
recommended that the D31-D0 pins do not have
network resistors connected. External resistors used
in the system design must be of a sufficient
resistance value to “flip” the level-keeper circuitry
and eliminate potential DC paths.
The level-keeper circuit is designed to allow an
external 27-K
pull-up resistor to switch the D31-D0
circuits to a logic-HIGH level even though the level-
keeper attempts to keep a logic-LOW level. In
general, pull-up resistors smaller than 27 K
can be
used as well as those greater than or equal to 1 M
.
Pull-down resistors, when connected to D31-D0,
should be least 800 K
.
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