- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377496 > INTEL486 SX (Intel Corp.) Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) PDF資料下載
參數(shù)資料
| 型號： | INTEL486 SX |
| 廠商： | Intel Corp. |
| 英文描述： | Emedded Ultra-Low Power INTEL486 SX Processor(嵌入式超低能量處理器) |
| 中文描述： | Emedded超低功耗英特爾486山西處理器（嵌入式超低能量處理器） |
| 文件頁數(shù)： | 21/38頁 |
| 文件大?。?/td> | 346K |
| 代理商： | INTEL486 SX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
17
Embedded Ultra-Low Power Intel486 SX Processor
4.2
Fast Clock Restart
The embedded ULP Intel486 SX processor has an
integrated proprietary differential delay line (DDL)
circuit for internal clock generation. The DDL is
driven by the CLK input signal provided by the
external system. During normal operation, the
external system must guarantee that the CLK signal
maintains its frequency so that the clock period
deviates no more than 250 ps/CLK. This state,
called the Normal State, is shown in Figure 4.
To increase or decrease the CLK frequency more
quickly than this, the system must interrupt the
processor with the STPCLK# signal. Once the
processor indicates that it is in the Stop Grant State,
the system can adjust the CLK signal to the new
frequency, wait a minimum of eight CLK periods,
then force the processor to return to the normal
operational state by deactivating the STPCLK#
interrupt. This wait of eight CLK periods is much
faster than the 1 ms wait required by earlier Intel486
SX processor products.
While in the Stop Grant State, the external system
may deactivate the CLK signal to the processor. This
forces the processor to the Stop Clock State — the
state in which the processor consumes the least
power. Once the system reactivates the CLK signal,
the processor transitions to the Stop Grant State
within eight CLK periods.
Normal operation can be resumed by deactivating
the STPCLK# interrupt signal. Here again, the
embedded ULP Intel486 SX processor recovers
from the Stop Clock State much faster than the 1 ms
PLL recovery of earlier Intel486 SX processors.
Figure 4. Stop Clock State Diagram with Typical Power Consumption Values
4 Auto HALT
Power Down State
CLK Running
40 - 85 mWatts
5 Stop Clock Snoop State
One Clock PowerUp
Perform Cache Invalidation
1 Normal State
Normal Execution
2 Stop Grant State
CLK Running
40 - 85 mWatts
3 Stop Clock State
Internal Powerdown
CLK Stopped
~ 60 μWatts
EADS#
STPCLK#
deasserted
Stop CLK
Start CLK
plus DDL Startup
Latency
STPCLK# asserted
and Stop Grant bus
cycle generated
STPCLK# asserted and
Stop Grant bus cycle generated
STPCLK# deasserted and
HALT bus cycle generated
HALT asserted and
HALT bus cycle
generated
INTR, NMI, SMI#
RESET, SRESET
EADS#
相關PDF資料 |
PDF描述 |
|---|---|
| INTEL82801 | 82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | Firmware Hub (FWH) |
| INTELDX2 | High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器) |
| INTELDX4 | Embedded Write-Back Enhanced Processor(32位回復嵌入式增強型處理器) |
| IPS54511 | FULLY PROTECTED HIGH SIDE POWER MOSFET SWITCH |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL740 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Graphics (GUI) Accelerator |
| INTEL82801 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82801AB (ICH0) I/O Controller Hub |
| INTEL82802AB | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Firmware Hub (FWH) |
| INTELLIGENT CHARGER + 4AA | 制造商:Energizer 功能描述:Bulk |
| INTELLI-INCH-LR-STARTER K | 制造商:ALL MOTION 功能描述:Intelli-Inch Stepper & Controller Starter Kit |
發(fā)布緊急采購，3分鐘左右您將得到回復。