參數(shù)資料
型號(hào)： intel Pentium CPU
廠商： Intel Corp.
英文描述： 32 Bit CPU With MMX Technology and Mobile Module(32位帶MMX和移動(dòng)模塊處理器)
中文描述： 32位CPU的MMX技術(shù)和移動(dòng)模塊（32位帶MMX公司和移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 8/36頁(yè)
文件大?。?/td> 395K
代理商： INTEL PENTIUM CPU
INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
8
1/8/98 4:35 PM 24351502.DOC
2.1.2.
PCI (56 SIGNALS)
Table 3 lists the
Intel Mobile Module’s PCI interface signals.
Table 3. PCI Signal Descriptions
Name
Type
Voltage
Description
AD[31:0]
I/O
V_3S
Address/Data:
The standard PCI address and data lines. The address is
driven with FRAME# assertion, and data is driven or received in following
clocks.
C/BE[3:0]#
I/O
V_3S
Command/Byte Enable:
The command is driven with FRAME# assertion,
and byte enables corresponding to supplied or requested data are driven on
following clocks.
FRAME#
I/O
V_3S
Frame:
Assertion indicates the address phase of a PCI transfer. Negation
indicates that one more data transfer is desired by the cycle initiator.
DEVSEL#
I/O
V_3S
Device Select:
This signal is driven by the 430TX PCIset when a PCI
initiator is attempting to access DRAM.
DEVSEL# is asserted at medium
decode time.
IRDY#
I/O
V_3S
Initiator Ready:
Asserted when the initiator is ready for data transfer.
TRDY#
I/O
V_3S
Target Ready:
Asserted when the target is ready for a data transfer.
STOP#
I/O
V_3S
Stop:
Asserted by the target to request the master to stop the current
transaction.
LOCK#
I/O
V_3S
Lock:
Used to establish, maintain and release resource locks on PCI.
REQ[3:0]#
I
V_3S
PCI Request:
PCI master requests for PCI.
GNT[3:0]#
O
V_3S
PCI Grant:
Permission is given to the master to use PCI.
*PHOLD#
I
V_3S
PCI Hold:
This signal comes from the expansion bridge; it is the bridge
request for PCI.
The 430TX PCIset will drain the DRAM write buffers, drain
the processor-to-PCI posting buffers, and acquire the host bus before
granting the request via PHLDA#. This ensures that GAT timing is met for
ISA masters.
The PHOLD# protocol has been modified to include support
for passive release.
*PHLDA#
O
V_3S
PCI Hold Acknowledge:
This signal is driven by the 430TX PCIset to grant
PCI to the expansion bridge.
The PHLDA# protocol has been modified to
include support for passive release.
PAR
I/O
V_3S
Parity:
A single parity bit is provided over AD[31:0] and C/BE[3:0]
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