參數(shù)資料
型號(hào)： intel Pentium CPU
廠商： Intel Corp.
英文描述： 32 Bit CPU With MMX Technology and Mobile Module(32位帶MMX和移動(dòng)模塊處理器)
中文描述： 32位CPU的MMX技術(shù)和移動(dòng)模塊（32位帶MMX公司和移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 10/36頁(yè)
文件大小： 395K
代理商： INTEL PENTIUM CPU
INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
10
1/8/98 4:35 PM 24351502.DOC
2.1.3.
PROCESSOR/PIIX4 ISA BRIDGE
SIDEBAND (9 SIGNALS)
Table 4 lists the
Intel Mobile Module’s processor
and PIIX4 ISA bridge sideband signals at the
Table 4. Processor/PIIX4 ISA Bridge Sideband Signal Descriptions
connector interface. (Refer to the PIIX4 ISA Bridge
External Architecture Specification (Order Number
290562-001) for complete signal descriptions and
detailed functions.) The voltage level for these
signals is determined by V_CPUIO, which is
supplied by the Intel Mobile Module.
Name
Type
Voltage
Description
FERR#
O
V_CPUIO
Numeric Coprocessor Error:
This pin functions as a FERR# signal
supporting coprocessor errors. This signal is tied to the coprocessor error
signal on the processor and is driven by the processor to the PIIX4 ISA
bridge.
NOTE:
This signal does NOT require a pull up on the system electronics. A pull up
is present on the Intel Mobile Module.
*CPURST
I
V_CPUIO
Processor Reset:
The PIIX4 ISA bridge asserts CPURST to reset the
processor. The PIIX4 ISA bridge asserts CPURST# during power-up and
when a hard reset sequence is initiated through the RC register.
*IGNNE#
I
V_CPUIO
Ignore Error:
This signal is connected to the ignore error pin on the
processor and is driven by the PIIX4 ISA bridge.
*INIT#
I
V_CPUIO
Initialization:
INIT is asserted by the PIIX4 ISA bridge to the processor
for system initialization.
NOTE:
The system manufacturer should provide a pull up/pull down option on this
pin, and connect this PIIX4 ISA bridge input to the Intel Mobile Module connector
PIN BB38.
Processor Interrupt:
INTR is driven by the PIIX4 ISA bridge to signal the
processor that an interrupt request is pending and needs to be serviced.
*INTR
I
V_CPUIO
*NMI
I
V_CPUIO
Non-Maskable Interrupt:
NMI is used to force a non-maskable interrupt
to the processor.
The PIIX4 ISA bridge generates an NMI when either
SERR# or IOCHK# is asserted, depending on how the NMI Status and
Control Register is programmed.
*A20M#
I
V_CPUIO
Address Bit 20 Mask:
When enabled, this causes the processor to
emulate the address wraparound at one Mbyte which occurs on the Intel
8086 processor.
*SMI#
I
V_CPUIO
System Management Interrupt:
SMI# is an active low synchronous
output that is asserted by the PIIX4 ISA bridge in response to one of many
enabled hardware or software events.
The SMI# signal can be an
asynchronous input to the processor.
However, in this chip set SMI# is
synchronous to PCLK.
*STPCLK#
I
V_CPUIO
Stop Clock:
STPCLK# is an active low synchronous output that is
asserted by the PIIX4 ISA bridge in response to one of many hardware or
software events.
STPCLK# connects directly to the processor and is
synchronous to PCLK.
When the processor samples STPCLK# asserted
it responds by stopping its internal clock.
* - These signals are open-drain and require a pull up resistor on the system electronics.
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