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參數(shù)資料
| 型號(hào)： | intel Pentium CPU |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit CPU With MMX Technology and Mobile Module(32位帶MMX和移動(dòng)模塊處理器) |
| 中文描述： | 32位CPU的MMX技術(shù)和移動(dòng)模塊（32位帶MMX公司和移動(dòng)模塊處理器） |
| 文件頁數(shù)： | 25/36頁 |
| 文件大?。?/td> | 395K |
| 代理商： | INTEL PENTIUM CPU |
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INTEL PENTIUM PROCESSOR WITH MMX TECHNOLOGY MOBILE MODULE
25
1/8/98 4:35 PM 24351502.DOC
3.4.3.
VOLTAGE SIGNAL DEFINITION AND SEQUENCING
Table 14. Voltage Signal Definitions and Sequences
Signal
Source
Definitions and Sequences
V_DC
System
Electronics
DC voltage driven from the power supply and is required to be between 5V and
20V DC +5% (maximum peak voltage is 21.1V including ripple). V_DC powers
the Intel Mobile Module’s DC-to-DC converter for processor core and I/O
voltages.
CAUTION: The Intel Mobile Module must not be inserted or removed while V_DC is
powered on.
V_3
System
Electronics
V_3 is supplied by the system electronics; the MTXC uses it during the
Suspend to DRAM state.
V_5
System
Electronics
V_5 is supplied by the system electronics. It is used by the Intel Mobile
Module’s voltage regulator.
V_3S
System
Electronics
V_3S are supplied by the system electronics for the processor, MTXC, and
cache devices. Each must be powered off during system Suspend-to-DRAM
and Suspend-to-Disk states, typically this signal is switched by a FET switch.
VR_ON
System
Electronics
This 3.3V signal controls the operation of the
Intel Mobile Module’s
voltage
regulator. This signal should be generated as a function of the PIIX4 SUSB#
signal. VR_ON should be timed to rise after the switch power planes have
stabilized. Please refer to section 3.4.2 for proper VR_ON sequencing.
NOTE:
The system electronics should subtract 6ms for the maximum latency of VR_ON
to V_CORE of the voltage regulator on the Intel Mobile Module.
V_CORE
Intel Mobile
Module Only
A result of VR_ON being asserted, V_CORE is an output of the DC-DC
regulator on the Intel Mobile Module and is driven to the appropriate voltage
level of the processor: 1.8 or 2.0.
VR_PWRGD
Intel Mobile
Module Only
Upon sampling the voltage level of V_CORE for the processor, minus
tolerances for ripple, VR_PWRGD is driven active high (3.3V) for the system
electronics to sample prior to providing PWROK to the PIIX4. If VR_PWRGD is
not sampled active within 1 second of the assertion of VR_ON the system
electronics should deassert VR_ON.
CAUTION
: This signal has an output impedance of approximately 100k
. Care must be
taken to prevent loading of this signal.
V_CPUIO
Intel Mobile
Module Only
V_CPUIO is 2.5V. The system electronics uses this voltage to power the PIIX4-
to-processor interface circuitry, as well as the HCLK_(0:1) drivers for the
SDRAM/OEM processor clock.
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