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參數(shù)資料

型號：	IDT88P8344BHGI
廠商：	INTEGRATED DEVICE TECHNOLOGY INC
元件分類：	微控制器/微處理器
英文描述：	SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述：	SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝：	GREEN, PLASTIC, BGA-820
文件頁數(shù)：	69/98頁
文件大?。?/td>	601K
代理商：	IDT88P8344BHGI

IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4

INDUSTRIAL TEMPERATURE RANGE

APRIL 10, 2006

TABLE 86 - SPI-4 INGRESS LP TO LID MAP

(256 ENTRIES, ONE PER LP)

Field

Bits

LID

PFP

ENABLE

There are 256 SPI-4 ingress LP to LID maps for the SPI-4 ingress interface

at Block_base 0x0000. The SPI-4 ingress LP to LID maps have read and write

access. The SPI-4 ingress LP to LID maps are used to map SPI-4 ingress logical

ports to logical identifiers used internally.

Data for an inactive LP having an entry in the calendar is forwarded to

LID0. Therefore all the LPs that have entries in the calendar tables should be

enabled.

Length

Initial Value

0x00

0x0

5:0

7:6

9.4.1 Common module block base 0x0000 registers

SPI-4 ingress LP to LID maps (Block_base 0x0000

+ Register_offset 0x00 to 0xFF)

LID

The LID programmed is associated to the LP with the same number

as the register address. Six bits support the 64 simultaneously active LIDs per

SPI-3 physical interface.

PFP

The PFP field is used to select among SPI-4 ingress to SPI-3 egress

Packet Processing Engines. The number in the PFP field selects the PFP

module to be used.

0x0=Select PFP Module A

0x1=Select PFP Module B

0x2=Select PFP Module C

0x3=Select PFP Module D

ENABLE

to a LID.

The Enable is used to enable or disable the connection of an LP

0=LP is disabled

1=LP is enabled

9.4.2 Common module block base 0x0100 registers

SPI-4 ingress calendar_0 (Block_base 0x0100 +

Register_offset 0x00 to 0xFF)

TABLE 87 - SPI-4 INGRESS CALENDAR_0

(256 ENTRIES)

Field

Bits

7:0

Length

Initial Value

0xFF

The SPI-4 ingress calendar_0 is at Block_base 0x0100 and has read and

write access. When the SPI-4 ingress calendar_0 is selected, SPI-4 ingress

calendar_0 is in use. There are 256 entries in the SPI-4 ingress calendar_0

to schedule the updating of the FIFO status channel LPs to the attached device.

If less than the maximum256 LPs are needed on the SPI-4 interface, the

calendar entries should be used for scheduling more frequent status updates

for higher-speed LPs. The value of time-critical LPs must appear multiple times

in the table. For example, a multi-PHY SPI-4 could have OC-48 channels

appear in the calendar at four times the rate of OC-12 channels, since the higher

data rate of the OC-48 channels would benefit frommore frequent FIFO status

channel updates. The LP field values range from0x00 to 0xFF. The

IDT88P8344 and the attached device must have identical calendars for ingress

and the attached egress device. The ingress and egress calendars of the

IDT88P8344 device do not have to match.

The LP value programmed schedules a status channel update

according to the calendar sequence.

9.4.3 Common module block base 0x0200 registers

SPI-4 ingress calendar_1 (Block_base 0x0200 +

Register_offset 0x00 to 0xFF)

TABLE 88 - SPI-4 INGRESS CALENDAR_1

(256 ENTRIES)

Field

Bits

7:0

Length

Initial Value

0xFF

The SPI-4 ingress calendar_1 is at Block_base 0x0200 and has read and

write access. When the SPI-4 ingress calendar_1 is selected, SPI-4 ingress

calendar_1 is in use. There are 256 entries in the SPI-4 ingress calendar_1