參數(shù)資料
型號: IDT88P8344BHGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝: GREEN, PLASTIC, BGA-820
文件頁數(shù): 18/98頁
文件大?。?/td> 601K
代理商: IDT88P8344BHGI
18
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Eye measurement
C[0]= Rt.D2^Rt.D3
C[1]= Rt.D3^Rt.D4
…..
C[7]= Rt.D9^Rt+1.D0
C[8]= Rt+1.D0^Rt+1.D1
C[9]= Rt+1.D1^Rt+1.D2
Accumulation results during a window defined by W are stored in the
diagnostics table.
The latest result can be read out for diagnostic purposes.
Output tap selection
The sampling tap is automatically selected based on the eye measurement.
Data sampling
The I_LOW field in the Table 89 SPI-4 ingress configuration register
(Block_base 0x0300 + Register_offset 0x00) selects an operating mode
between 80 MHz and 200 MHz or between 200 MHz and 400 MHz.
Each lane is over-sampled by a factor of five. The over-sampled data is
generated by a locked tapped delay line and clocked in to a register at the clock
rate. The current samples c(n) and the previously generated samples provide
samples for the eye computation. The optimzed sampling point will be selected
based on the eye computation. The tap selector is updated if necessary at the
end of the eye pattern measurement interval. The tap selector moves no more
than one tap at a time as a result of the eye pattern measurement.
CLK
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
Data
CLK
D0
D1
D9
D0
D2
D3
D4
D5
D8
D7
D6
D9
D8
D7
D6
D5
D4
D3
D2
D1
R(t+1)
R(t)
Figure 7. Data sampling diagram
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