參數(shù)資料
型號： IDT88P8344BHGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝： GREEN, PLASTIC, BGA-820
文件頁數(shù)： 59/98頁
文件大?。?/td> 601K
代理商： IDT88P8344BHGI
59
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
TABLE 56 - SPI-4 INGRESS TO SPI-3 EGRESS FLOW
CONTROL REGISTER (REGISTER_OFFSET=0x01)
Field
Bits
CREDIT_EN
0
BURST_EN
1
LOOP_BACK
2
Reserved
31:3
The SPI-4 ingress to SPI-3 egress flow control register has read and write
access. The bit fields of the SPI-4 ingress to SPI-3 egress flow control register
are described.
Length
1
1
1
29
Initial Value
0b0
0b0
0b0
0x00
TABLE 57 - SPI-3 EGRESS TEST REGISTER
(REGISTER_OFFSET=0x02)
Field
Bits
ADD_PAR_ERR
0
DAT_PAR_ERR
1
Reserved
7:2
PORT_ADDRESS
15:8
Length
1
1
6
8
Initial Value
0b0
0b0
0x00
0x0F
ENABLE
an LP.
This bit is used to enable or disable the connection of a LID to
0=LP disabled
1=LP enabled
BIT_REVERSAL
This bit is used to reverse the bit ordering of each byte
of the SPI-3 interface on a per-LP basis.
0=Disable bit reversal for an LP
1=Enable bit reversal for an LP
9.3.4 Block base 0x0700 registers
SPI-3 egress configuration register (Block_base
0x0700 + Register_offset 0x00)
TABLE 55 - SPI-3 EGRESS CONFIGURATION
REGISTER (REGISTER_OFFSET=0x00)
Field
Bits
POLL_LENGTH
5:0
Reserved
7:6
STX_SPACING
8
EOP_SPACING
9
Reserved
31:10
There is one SPI-3 egress configuration register per SPI-3 interface. The
SPI-3 egress configuration registers have read and write access. A SPI-3
egress configuration registers is used to control the poll sequence length of a
SPI-3 egress interface when the SPI-3 interface is in Link mode. The SPI-3
egress configuration register is used to add two cycles to STX or EOP as
required to interface to the attached device.
POLL_LENGTH
Poll sequence length when in Link mode. The poll
sequence is fromthe LP associated with LID0 to the LP associated with the LID
for POLL_LENGTH - 1.
STX_SPACING
This bit is used to enable or disable the adding of two
dummy STX cycles to a SPI-3 egress interface to meet the needs of an attached
device.
0= No dummy STX cycles are added to a SPI-3 egress.
1= Two dummy STX cycles are added to a SPI-3 egress
EOP_SPACING
This bit is used to enable or disable the adding of two
dummy EOP cycles to a SPI-3 egress interface to meet the needs of an attached
device.
0= No dummy EOP cycles are added to a SPI-3 egress.
1= Two dummy EOP cycles are added to a SPI-3 egress
SPI-4 ingress to SPI-3 egress flow control register
(Block_base 0x0700 + Register_offset 0x01)
CREDIT_EN
the attached SPI-3 device is interpreted as status or credit information as selected
by the CREDIT_EN bit in the SPI-4 ingress to SPI-3 egress flow control Register.
If the status mode is used, data will be egressed until the status is changed by
the attached SPI-3 device. If the credit mode is used, the SPI-3 egress will
transmt only one packet fragment and then wait for an update in the internal buffer
segment pool status before sending another packet fragment.
0=Status mode
1=Credit mode
CREDIT_EN The flow control information received from
BURST_EN
to an LP. When this feature is not enabled, only one burst per LP is allowed into
the SPI-3 egress buffers.
0=Disable burst enable
1=Enable burst enable
Multiple Burst Enable allows more than one burst to be sent
LOOP_BACK
transferred to a SPI-3 egress buffers of the same port. This mode is useful for
off-line diagnostics.
0=Disable loopback
1=Enable loopback
In this mode the contents of a SPI-3 ingress are directly
SPI-3 egress test register (Block_base 0x0700 +
Register_offset 0x02)
Length
6
2
1
1
22
Initial Value
0x0F
0b00
0b0
0b0
0x00
The SPI-3 egress test register has read and write access. A single address
parity error is introduced on a SPI-3 egress LP through the ADD_PAR_ERR
bit field. A single data parity error is introduced on a SPI-3 egress LP through
the DAT_PAR_ERR bit field. The LP affected by these two parity error bit fields
is enumerated in the PORT_ADDRESS field. The bit fields of SPI-3 egress test
register are described. The bit fields are automatically cleared following the
generation of the associated error.
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