參數(shù)資料
型號: IDT88P8344BHGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝: GREEN, PLASTIC, BGA-820
文件頁數(shù): 16/98頁
文件大?。?/td> 601K
代理商: IDT88P8344BHGI
16
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
6370 drw39
IDT88P8344
(PHY MODE)
LINK
E_FCLK
E_MOD[1:0]
E_SOP
E_ENB
E_EOP
E_RSX
E_PRTY
E_Data[31:0]
E_ERR
RVAL
Figure 6. PHY mode SPI-3 egress interface
byte mode
packet mode
6370 drw38
IDT88P8344
(LINK MODE)
PHY
E_FCLK
E_MOD[1:0]
E_SOP
E_ENB
E_PRTY
E_Data[31:0]
E_ERR
ADDR[7:0]
PTPA
DTPA[3:0]
STPA
E_EOP
E_RSX
Figure 5. Link mode SPI-3 egress interface
SPI-3 egress Link mode
The SPI Exchange receives status information fromthe PHY. The PHY
indicates its ability to receive data. Status information for all logical ports is directed
towards the packet fragment processor.
Status information is received fromthe PHY.
In packet mode, the SPI Exchange polls the PHY for the logical ports
associated to LIDs ranging from0 up to POLL_LENGTH to find logical ports that
can accept data. The POLL_LENGTH field is defined in the SPI-3 egress
configuration register.
In byte mode the SPI Exchange allows for direct status detection.
This status information is directly forwarded to the packet fragment proces-
sor if enabled by the BURST_EN flag. When the BURST_EN flag is cleared
the only one packet fragment per LP is allowed into the SPI-3 egress buffers.
SPI-3 egress PHY mode
In PHY mode, the SPI Exchange sends data to the attached Link-mode device
as long as the E_ENB signal is asserted. The SPI-3 packet fragment processor
transfers data to the SPI-3 egress buffers.
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