參數(shù)資料
型號(hào)： IDT88P8344BHGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820
封裝： GREEN, PLASTIC, BGA-820
文件頁(yè)數(shù)： 14/98頁(yè)
文件大?。?/td> 601K
代理商： IDT88P8344BHGI
14
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Figure 3. Link mode SPI-3 ingress interface
IDT88P8344
(LINK MODE)
PHY
I_FCLK
I_MOD[1:0]
6370 drw25
I_RSX
I_ENB
I_EOP
I_SOP
RVAL
I_PRTY
I_Data[31:0]
I_ERR
Figure 4. PHY mode SPI-3 ingress interface
byte mode
packet mode
6370 drw26
IDT88P8344
(PHY MODE)
LINK
I_FCLK
I_MOD[1:0]
I_SOP
I_ENB
I_PRTY
I_Data[31:0]
I_ERR
ADDR[7:0]
PTPA
DTPA[3:0]
STPA
I_EOP
I_RSX
SPI-3 ingress Link mode
Refer to [Glossary] for details about the SPI-3 interface.
The PHY pushes data into the device in blocks from1 up to 256 bytes.
The SPI Exchange provides backpressure for the SPI-3 ingress physical
interface by the I_ENB signal. The I_ENB is asserted when at least one
active LID can not accept data. This feature is enabled by the
BACKPRESSURE_EN flag in the SPI-3 ingress configuration register
(register_offset = 0x01). When the flag is cleared the I_ENB signal will not be
asserted, hence no backpressure can be generated.
SPI-3 ingress PHY mode
The SPI Exchange indicates to the Link layer it has buffer space available
by proper response to either Link layer polling (packet mode ) or direct indication
on DTPA signals (byte mode). The selection is made by the PACKET flag in
the SPI-3 configuration register.
In packet mode the device responds to polling (by Link layer device)
In byte mode the direct status indication is limted to 4 addresses (fixed ports
[3:0])
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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