參數(shù)資料
型號: IDT82V2082BFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 63/88頁
文件大小: 0K
描述: IC LIU T1/E1/J1 2CH 81BGA
標(biāo)準(zhǔn)包裝: 360
類型: 線路接口裝置(LIU)
規(guī)程: T1,E1,J1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 81-LFBGA
供應(yīng)商設(shè)備封裝: 81-CABGA(8x8)
包裝: 托盤
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
IEEE STD 1149.1 JTAG TEST ACCESS PORT
66
May 4, 2009
6
IEEE STD 1149.1 JTAG TEST ACCESS PORT
The IDT82V2082 supports the digital Boundary Scan Specification as
described in the IEEE 1149.1 standards.
The boundary scan architecture consists of data and instruction regis-
ters plus a Test Access Port (TAP) controller. Control of the TAP is per-
formed through signals applied to the Test Mode Select (TMS) and Test
Clock (TCK) pins. Data is shifted into the registers via the Test Data Input
(TDI) pin, and shifted out of the registers via the Test Data Output (TDO)
pin. Both TDI and TDO are clocked at a rate determined by TCK.
The JTAG boundary scan registers include BSR (Boundary Scan Reg-
ister), IDR (Device Identification Register), BR (Bypass Register) and IR
(Instruction Register). These will be described in the following pages. Refer
to Figure-22 for architecture.
Figure-22 JTAG Architecture
BSR (Boundary Scan Register)
IDR (Device Identification Register)
BR (Bypass Register)
IR (Instruction Register)
MUX
TDO
TDI
TCK
TMS
TRST
Control<6:0>
MU
X
Select
high impedance enable
TAP
(Test Access Port)
Controller
parallel latched output
Digital output pins
Digital input pins
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