Figure-9 Transmit/Receive Line Circ" />
參數(shù)資料
型號(hào): IDT82V2082BFG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 20/88頁(yè)
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 2CH 81BGA
標(biāo)準(zhǔn)包裝: 360
類型: 線路接口裝置(LIU)
規(guī)程: T1,E1,J1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 81-LFBGA
供應(yīng)商設(shè)備封裝: 81-CABGA(8x8)
包裝: 托盤
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
27
May 4, 2009
Figure-9 Transmit/Receive Line Circuit
In hardware control mode, TERMn, PULSn[3:0] pins can be used to
select impedance matching for both receiver and transmitter on a per chan-
nel basis. If TERMn pin is low, internal impedance network will be used. If
TERMn pin is high, external impedance network will be used in E1 mode,
or external impedance network for receiver and internal impedance net-
work for transmitter will be used in T1/J1 mode. (This applies to ZB die revi-
sion only). When internal impedance network is used, PULSn[3:0] pins
should be set to select specific internal impedance for the corresponding
channel. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.4.2
LINE MONITOR
In both T1/J1 and E1 short haul applications, the non-intrusive monitor-
ingonchannelslocatedinotherchipscanbeperformedbytappingthemon-
itored channel through a high impedance bridging circuit. Refer to Figure-
After a high resistance bridging circuit, the signal arriving at the RTIPn/
RRINGn is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selected by MG[1:0] bits (RCF2, 0BH...). For normal operation, the Monitor
Gain should be set to 0 dB.
In hardware control mode, MONTn pin can be used to set the Monitor
Gain on a per channel basis. When MONTn pin is low, the Monitor Gain for
the specific channel is 0 dB. When MONTn pin is high, the Monitor Gain for
the specific channel is 26 dB. Refer to 5 HARDWARE CONTROL PIN SUM-
for details.
Figure-10 Monitoring Receive Line in Another Chip
Figure-11 Monitor Transmit Line in Another Chip
Note:
1. Common decoupling capacitor. One per chip
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060
4. RT/ RR: refer toTable-14 and Table-15 respecivley for RT and RR values
A
B
RX Line
RR4
TX Line
RT4
RTIPn
RRINGn
TRINGn
TTIPn
0.1
F
GNDTn
VDDTn
IDT
82V2082
VDDTn
D4
D3
D2
D1
1:1
2:1
68
F1
D6
D5
D8
D7
Cp
VDDRn
One of the Two Identical Channels
2
3
3.3 V
0.1
F
GNDRn
VDDRn
68
F
3.3 V
1
RTIP
RRING
RTIP
RRING
normal receive mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
monitor
gain=0dB
TTIP
TRING
RTIP
RRING
normal transmit mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
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