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參數(shù)資料
| 型號： | IDT82V2082BFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 54/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 2CH 81BGA |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 81-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 81-CABGA（8x8） |
| 包裝： | 托盤 |
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IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION
58
May 4, 2009
Table-48 INTES: Interrupt Trigger Edge Select Register
(R/W, Address = 15H, 35H)
Symbol
Bit
Default
Description
EQ_IES
7
0
This bit determines the Equalizer out of range interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the EQ_S bit in the STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the EQ_S bit in the STAT0
status register.
IBLBA_IES
6
0
This bit determines the Inband Loopback Activate Code interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBA_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBA_S bit in STAT0
status register
IBLBD_IES
5
0
This bit determines the Inband Loopback Deactivate Code interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBD_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBD_S bit in STAT0
status register
PRBS_IES
4
0
This bit determines the PRBS/QRSS synchronization status interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the PRBS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in STAT0
status register
TCLK_IES
3
0
This bit determines the TCLK Loss interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in STAT0
status register
DF_IES
2
0
This bit determines the Driver Failure interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the DF_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in STAT0 status
register
AIS_IES
1
0
This bit determines the AIS interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the AIS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in STAT0 status
register
LOS_IES
0
This bit determines the LOS interrupt event.
= 0: Interrupt is generated as a ‘0’ to ‘1’ transition of the LOS_S bit in STAT0 status register
= 1: Interrupt is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in STAT0 status
register
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V2082BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 2CH 81BGA |
| IDT82V2082BFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082PF | 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082PF8 | 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082PFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
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