參數(shù)資料
型號(hào)： IDT82V2082BFG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 24/88頁(yè)
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 2CH 81BGA
標(biāo)準(zhǔn)包裝： 360
類型： 線路接口裝置（LIU）
規(guī)程： T1，E1，J1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 81-LFBGA
供應(yīng)商設(shè)備封裝： 81-CABGA（8x8）
包裝： 托盤
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
30
May 4, 2009
3.5
JITTER ATTENUATOR
ThereisoneJitterAttenuatorineachchanneloftheLIU.TheJitterAtten-
uator can be deployed in the transmit path or the receive path, and can also
be disabled. This is selected by the JACF[1:0] bits (JACF, 03H...).
In hardware control mode, Jitter Attenuator position, bandwidth and the
depth of FIFO can be selected by JA[1:0] pins on a global basis. Refer to 5
for details.
3.5.1
JITTER ATTENUATION FUNCTION DESCRIPTION
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
Figure-13. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF,03H...).Inhardwarecontrolmode,thedepthofFIFOcanbeselected
by JA[1:0]pinson aglobalbasis. Referto 5HARDWARECONTROLPINSUM-
for details. Consequently, the constant delay of the Jitter Attenuator
will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but
at the cost of increasing data latency time.
Figure-13 Jitter Attenuator
In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or
6.8 Hz, as selected by the JABW bit (JACF, 03H...). In T1/J1 applications,
the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected
by the JABW bit (JACF, 03H...). The lower the Corner Frequency is, the
longer time is needed to achieve synchronization.
When the incoming data moves faster than the outgoing data, the FIFO
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 19H...).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the JAUD_IS bit (INTS1, 19H...).
For some applications that are sensitive to data corruption, the JA limit
mode can be enabled by setting JA_LIMIT bit (JACF, 03H...) to ‘1’. In the
JA limit mode, the speed of the outgoing data will be adjusted automatically
when the FIFO is close to its full or emptiness. The criteria of starting speed
adjustment are shown in Table-16. The JA limit mode can reduce the pos-
sibility of FIFO overflow and underflow, but the quality of jitter attenuation
is deteriorated.
3.5.2
JITTER ATTENUATOR PERFORMANCE
The performance of the Jitter Attenuator in the IDT82V2082 meets the
ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/
13, AT&T TR62411 specifications. Details of the Jitter Attenuator perfor-
FIFO
32/64/128
DPLL
Jittered Data
De-jittered Data
Jittered Clock
De-jittered Clock
MCLK
W
R
RCLKn
RDn/RDPn
RDNn
Table-16 Criteria of Starting Speed Adjustment
FIFO Depth
Criteria for Adjusting Data Outgoing Speed
32 Bits
2 bits close to its full or emptiness
3 bits close to its full or emptiness
4 bits close to its full or emptiness
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