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參數(shù)資料
| 型號： | IDT82V2082BFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 19/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 2CH 81BGA |
| 標準包裝： | 360 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 81-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 81-CABGA（8x8） |
| 包裝： | 托盤 |
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IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
26
May 4, 2009
3.3.5
TRANSMIT PATH POWER DOWN
The transmit path can be powered down individually by setting the
T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
In hardware control mode, the transmit path can be powered down by
setting PATTn[1:0] pins to ‘11’ on a per channel basis. Refer to 5 HARD-
for details.
3.4
RECEIVE PATH
The receive path consists of Receive Internal Termination, Monitor
Gain,Amplitude/WaveShapeDetector,DigitalTuningController,Adaptive
Equalizer, DataSlicer,CDR(Clock &Data Recovery),OptionalJitter Atten-
uator, Decoder and LOS/AIS Detector. Refer to Figure-8.
3.4.1
RECEIVE INTERNAL TERMINATION
The impedance matching can be realized by the internal impedance
matching circuit or the external impedance matching circuit. If R_TERM[2]
is set to ‘0’, the internal impedance matching circuit will be selected. In this
case, the R_TERM[1:0] bits (TERM, 02H...) can be set to choose 75
,100
, 110 or 120 internal impedance of RTIPn/RRINGn. If R_TERM[2]
is set to ‘1’, the internal impedance matching circuit will be disabled. In this
case, the external impedance matching circuit will be used to realize the
impedance matching.
Figure-9 shows the appropriate external components to connect with
the cable for one channel. Table-15 is the list of the recommended imped-
ance matching for receiver.
Figure-8 Receive Path Function Block Diagram
Table-15 Impedance Matching for Receiver
Cable Configuration
Internal Termination
External Termination
R_TERM[2:0]
RR
R_TERM[2:0]
RR
E1/75
000
120
1XX
75
E1/120
001
120
T1
010
100
J1
011
110
Monitor Gain/
Adaptive Equalizer
LOS/AIS
Detector
Data Slicer
Decoder
LOS
RCLK
RDP
RDN
RTIP
Clock
and Data
Recovery
Receive
Internal
termination
RRING
Jitter
Attenuator
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V2082BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 2CH 81BGA |
| IDT82V2082BFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082PF | 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082PF8 | 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082PFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
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