參數(shù)資料
型號(hào): IDT82V2052EPFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 57/70頁
文件大?。?/td> 0K
描述: IC LIU E1 2CH SHORT HAUL 80-TQFP
標(biāo)準(zhǔn)包裝: 45
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 托盤
其它名稱: 82V2052EPFG
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
TEST SPECIFICATIONS
60
December 12, 2005
1.Relative to nominal frequency, MCLK= ± 100 ppm
2.RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement
for E1 per ITU G.823).
3.For all digital outputs. C load = 15pF
Figure-21 Transmit System Interface Timing
Table-51 Transmitter and Receiver Timing Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
MCLK frequency
2.048
MHz
MCLK tolerance
-100
100
ppm
MCLK duty cycle
30
70
%
Transmit path
TCLK frequency
2.048
MHz
TCLK tolerance
-50
+50
ppm
TCLK Duty Cycle
10
90
%
t1
Transmit Data Setup Time
40
ns
t2
Transmit Data Hold Time
40
ns
Delay time of THZ low to driver high impedance
10
us
Delay time of TCLK low to driver high impedance
75
U.I.
Receive path
Clock recovery capture range 1
± 80
ppm
RCLK duty cycle 2
40
50
60
%
t4
RCLK pulse width 2
457
488
519
ns
t5
RCLK pulse width low time
203
244
285
ns
t6
RCLK pulse width high time
203
244
285
ns
Rise/fall time 3
20
ns
t7
Receive Data Setup Time
200
244
ns
t8
Receive Data Hold Time
200
244
ns
TDNn
TDn/TDPn
TCLKn
t1
t2
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