參數(shù)資料
型號： IDT82V2052EPFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 28/70頁
文件大?。?/td> 0K
描述： IC LIU E1 2CH SHORT HAUL 80-TQFP
標(biāo)準(zhǔn)包裝： 45
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-TQFP（14x14）
包裝： 托盤
其它名稱： 82V2052EPFG
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
34
December 12, 2005
3.12 INTERRUPT HANDLING
All kinds of interrupt of the IDT82V2052E are indicated by the INT pin.
When the INT_PIN[0] bit (GCF, 20H) is ‘0’, the INT pin is open drain active
low, with a 10 K
external pull-up resistor. When the INT_PIN[1:0] bits
(GCF, 20H) are ‘01’, the INT pin is push-pull active low; when the
INT_PIN[1:0] bits are ‘10’, the INT pin is push-pull active high.
AlltheinterruptcanbedisabledbytheINTM_GLBbit(GCF,20H).When
the INTM_GLB bit (GCF, 20H) is set to ‘0’, an active level on the INT pin
represents an interrupt of the IDT82V2052E. The INT_CH[1:0] (GCF, 20H)
should be read to identify which channel(s) generate the interrupt.
The interrupt event is captured by the corresponding bit in the Interrupt
Status Register (INTS0, 18H...) or (INTS1, 19H...). Every kind of interrupt
canbeenabled/disabledindividuallybythecorresponding bitinthe register
(INTM0, 13H...) or (INTM1, 14H...). Some event is reflected by the corre-
sponding bit in the Status Register (STAT0, 16H...) or (STAT1, 17H...), and
theInterruptTriggerEdgeSelectionRegistercanbeusedtodeterminehow
the Status Register sets the Interrupt Status Register.
After the Interrupt Status Register (INTS0, 18H...) or (INTS1, 19H...) is
read, the corresponding bit indicating which channel generates the inter-
rupt in the INTCH register (21H) will be reset. Only when all the pending
interrupt is acknowledged through reading the Interrupt Status Registers
of all the channels (INTS0, 18H...) or (INTS1, 19H...) will all the bits in the
INTCH register (21H) be reset and the INT pin become inactive.
Therearetotallytwelvekindsofeventsthatcouldbetheinterruptsource
for one channel:
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).One-Second Timer Expired
(11). Error Counter Overflow
(12).Arbitrary Waveform Generator Overflow
Table-12 is a summary of all kinds of interrupt and the associated Status
bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt
Mask bit.
Table-12 Interrupt Event
Interrupt Event
Status bit
(STAT0, STAT1)
Interrupt Status bit
(INTS0, INTS1)
Interrupt Edge Selection
bit
(INTES)
Interrupt Mask bit
(INTM0, INTM1)
LOS Detected
LOS_S
LOS_IS
LOS_IES
LOS_IM
AIS Detected
AIS_S
AIS_IS
AIS_IES
AIS_IM
Driver Failure Detected
DF_S
DF_IS
DF_IES
DF_IM
TCLK Loss
TCLK_LOS
TCLK_LOS_IS
TCLK_IES
TCLK_IM
Synchronization Status of PRBS
PRBS_S
PRBS_IS
PRBS_IES
PRBS_IM
PRBS Error
ERR_IS
ERR_IM
Code Violation Received
CV_IS
CV_IM
Excessive Zeros Received
EXZ_IS
EXZ_IM
JA FIFO Overflow
JAOV_IS
JAOV_IM
JA FIFO Underflow
JAUD_IS
JAUD_IM
One-Second Timer Expired
TMOV_IS
TIMER_IM
Error Counter Overflow
CNT_OV_IS
CNT_IM
Arbitrary Waveform Generator Overflow
DAC_OV_IS
DAC_OV_IM
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