Figure-7 Monitoring Receive Line in Another " />
參數(shù)資料
型號: IDT82V2052EPFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/70頁
文件大?。?/td> 0K
描述: IC LIU E1 2CH SHORT HAUL 80-TQFP
標準包裝: 45
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-TQFP(14x14)
包裝: 托盤
其它名稱: 82V2052EPFG
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
22
December 12, 2005
Figure-7 Monitoring Receive Line in Another Chip
Figure-8 Monitor Transmit Line in Another Chip
3.3.3
ADAPTIVE EQUALIZER
The Adaptive Equalizer can be enabled to increase the receive sensi-
tivity and to allow programming of the LOS level up to -24 dB. See section
3.5 LOS AND AIS DETECTION. It can be enabled or disabled by setting
EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0AH...).
3.3.4
RECEIVE SENSITIVITY
InHostmode,theReceiveSensitivityis-10dB.WiththeAdaptiveEqual-
izer enabled, the receive sensitivity will be -20 dB.
In Hardware mode, the Adaptive Equalizer can not be enabled and the
receive sensitivity is fixed at -10 dB. Refer to 5 HARDWARE CONTROL PIN
for details.
3.3.5
DATA SLICER
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
0BH...).The outputofthe Data Slicer is forwarded totheCDR (Clock& Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
3.3.6
CDR (Clock & Data Recovery)
The CDR is used to recover the clock and data from the received signal.
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absence of the incoming pulse. The CDR can also be by-passed in the Dual
Rail mode. When CDR is by-passed, the data from the Data Slicer is output
to the RDPn/RDNn pins directly.
3.3.7
DECODER
The R_MD[1:0] bits (RCF0, 09H...) are used to select the AMI decoder
or HDB3 decoder.
When the chip is configured by hardware, the operation mode of receive
and transmit path can be selected by setting RXTXM[1:0] pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.3.8
RECEIVE PATH SYSTEM INTERFACE
The receive path system interface consists of RCLKn pin, RDn/RDPn
pin and RDNn pin. The RCLKn outputs a recovered 2.048 MHz clock. The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/
RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...).
In hardware control mode, only the active edge of RCLKn can be
selected.IfRCLKEissettohigh,thefallingedgewillbechosenastheactive
edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as
the active edge of RCLKn. The active level of the data on RDn/RDPn and
RDNn is the same as that in software control mode.
Thereceiveddatacanbeoutputtothesystemsideintwodifferentways:
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Sin-
gle Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
RTIP
RRING
RTIP
RRING
normal receive mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
monitor
gain=0dB
TTIP
TRING
RTIP
RRING
normal transmit mode
monitor mode
DSX cross connect
point
R
monitor gain
=22/26/32dB
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