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| 型號： | IDT82V2052EPFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 20/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1 2CH SHORT HAUL 80-TQFP |
| 標(biāo)準包裝： | 45 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2052EPFG |
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
27
December 12, 2005
3.6
TRANSMIT AND DETECT INTERNAL PATTERNS
Theinternal patterns(AllOnes,All Zeros andPRBS pattern) will be gen-
erated and detected by IDT82V2052E. TCLKn is used as the reference
clock by default. MCLK can also be used as the reference clock by setting
the PATT_CLK bit (MAINT0, 0CH...) to ‘1’.
If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘0’ and the PATT[1:0] bits
(MAINT0, 0CH...) are set to ‘00’, the transmit path will operate in normal
mode.
When the chip is configured by hardware, the transmit path will operate
in normal mode by setting PATTn[1:0] pins to ‘00’ on a per channel basis.
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.6.1
TRANSMIT ALL ONES
In transmit direction, the All Ones data can be inserted into the data
stream when the PATT[1:0] bits (MAINT0, 0CH...) are set to ‘01’. The trans-
mit data stream is output from TTIPn/TRINGn. In this case, either TCLKn
or MCLK can be used as the transmit clock, as selected by the PATT_CLK
bit (MAINT0, 0CH...).
Inhardwarecontrolmode,theAllOnesdatacanbeinsertedintothedata
stream in transmitdirectionby settingPATTn[1:0] pins to ‘01’ on aperchan-
nel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.6.2
TRANSMIT ALL ZEROS
If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘1’, the All Zeros will be
inserted into the transmit data stream when the PATT[1:0] bits (MAINT0,
0CH...) are set to ‘00’.
3.6.3
PRBS GENERATION AND DETECTION
A PRBS will be generated in the transmit direction and detected in the
receive direction by IDT82V2052E. The PRBS is 215-1, with maximum zero
restrictions according to ITU-T O.151.
WhenthePATT[1:0]bits(MAINT0,0CH...)aresetto‘10’,thePRBSpat-
tern will be inserted into the transmit data stream with the MSB first. The
PRBS pattern will be transmitted directly or invertedly.
In hardware control mode, the PRBS data will be generated in the trans-
mit direction and inserted into the transmit data stream by setting
PATTn[1:0] pins to ‘10’ on a per channel basis. Refer to 5 HARDWARECON-
for details.
The PRBS in the received data stream will be monitored. If the PRBS
has reached synchronization status, the PRBS_S bit (STAT0, 16H...) will
be set to ‘1’, even in the presence of a logic error rate less than or equal to
PRBS data canbe inverted throughsetting the PRBS_INVbit(MAINT0,
0CH...).
Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,
18H...). The PRBS_IES bit (INTES, 15H...) can be used to determine
whetherthe ‘0’ to‘1’changeof PRBS_Sbitwill becapturedby thePRBS_IS
bitoranychangesofPRBS_SbitwillbecapturedbythePRBS_ISbit.When
the PRBS_IS bit is ‘1’, an interrupt will be generated if the PRBS_IM bit
(INTM0, 13H...) is set to ‘1’.
The received PRBS logic errors can be counted in a 16-bit counter if the
ERR_SEL [1:0] bits (MAINT6, 12H...) are set to ‘00’. Refer to 3.8 ERROR
DETECTION/COUNTING AND INSERTION for the operation of the error
counter.
3.7
LOOPBACK
To facilitate testing and diagnosis, the IDT82V2052E provides three dif-
ferent loopback configurations: Analog Loopback, Digital Loopback and
Remote Loopback.
3.7.1
ANALOG LOOPBACK
WhentheALPbit(MAINT1,0DH...)issetto‘1’,thecorrespondingchan-
nel is configured in Analog Loopback mode. In this mode, the transmit sig-
nals are looped back to the Receiver Internal Termination in the receive
path then output from RCLKn, RDn, RDPn/RDNn. The all-ones pattern can
be generated during analog loopback. At the same time, the transmit sig-
nalsarestilloutputtoTTIPn/TRINGnintransmitdirection.Figure-12shows
the process.
In hardware control mode, Analog Loopback can be selected by setting
LPn[1:0] pins to ‘01’ on a per channel basis.
3.7.2
DIGITAL LOOPBACK
WhentheDLPbit(MAINT1,0DH...)issetto‘1’,thecorrespondingchan-
nel is configured in Digital Loopback mode. In this mode, the transmit sig-
nals are looped back to the jitter attenuator (if enabled) and decoder in
receive path, then output from RCLKn, RDn, RDPn/RDNn. At the same
time, the transmit signals are still output to TTIPn/TRINGn in transmit direc-
tion. Figure-13 shows the process.
Both Analog Loopback mode and Digital Loopback mode allow the
sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will
overwrite the transmit signals. In this case, either TCLKn or MCLK can be
used as the reference clock for internal patterns transmission.
In hardware control mode, Digital Loopback can be selected by setting
LPn[1:0] pins to ‘10’ on a per channel basis.
3.7.3
REMOTE LOOPBACK
WhentheRLPbit(MAINT1,0DH...)issetto‘1’,thecorrespondingchan-
nel is configured in Remote Loopback mode. In this mode, the recovered
clock and data output from Clock and Data Recovery on the receive path
is looped back to the jitter attenuator (if enabled) and Waveform Shaper in
transmit path. Figure-14 shows the process.
Inhardwarecontrolmode,RemoteLoopbackcanbeselectedbysetting
LPn[1:0] pins to ‘11’ on a per channel basis.
Table-10 Criteria for Setting/Clearing the PRBS_S Bit
PRBS Detection 6 or less than 6 bit errors detected in a 64 bits hopping win-
dow.
PRBS Missing More than 6 bit errors detected in a 64 bits hopping window.
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