參數(shù)資料
型號: IDT82V2052EPFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 33/70頁
文件大?。?/td> 0K
描述: IC LIU E1 2CH SHORT HAUL 80-TQFP
標準包裝: 45
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設備封裝: 80-TQFP(14x14)
包裝: 托盤
其它名稱: 82V2052EPFG
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION
39
December 12, 2005
4.3.2
TRANSMIT AND RECEIVE TERMINATION REGISTER
4.3.3
JITTER ATTENUATION CONTROL REGISTER
Table-19 TERM: Transmit and Receive Termination Configuration Register
(R/W, Address = 02H, 22H)
Symbol
Bit
Default
Description
-
7-6
00
Reserved.
T_TERM[2:0]
5-3
000
These bits select the internal termination for transmit line impedance matching.
= 000: Internal 75
impedance matching
= 001: Internal 120
impedance matching
= 010 / 011: Reserved
= 1xx: Selects external impedance matching resistors (see Table-4).
R_TERM[2:0]
2-0
000
These bits select the internal termination for receive line impedance matching.
= 000: Internal 75
impedance matching
= 001: Internal 120
impedance matching
= 010 / 011: Reserved
= 1xx: Selects external impedance matching resistors (see Table-5).
Table-20 JACF: Jitter Attenuation Configuration Register
(R/W, Address = 03H, 23H)
Symbol
Bit
Default
Description
-
7-6
00
Reserved.
JA_LIMIT
5
1
= 0: Normal mode
= 1: JA limit mode
JACF[1:0]
4-3
00
Jitter Attenuation configuration
= 00/10: JA not used
= 01: JA in transmit path
= 11: JA in receive path
JADP[1:0]
2-1
00
Jitter Attenuation depth select
= 00: 128 bits
= 01: 64 bits
= 1x: 32 bits
JABW
0
Jitter transfer function bandwidth select
= 0: 6.8 Hz
= 1: 0.9 Hz
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