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參數(shù)資料
| 型號： | IDT82V2052EPFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 26/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1 2CH SHORT HAUL 80-TQFP |
| 標(biāo)準(zhǔn)包裝： | 45 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | 82V2052EPFG |
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
32
December 12, 2005
3.10 MCLK AND TCLK
3.10.1 MASTER CLOCK (MCLK)
MCLK is an independent, free-running reference clock. MCLK is 2.048
MHz. This reference clock is used to generate several internal reference
signals:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
Reference clock during Transmit All Ones (TAOS), all zeros and
PRBS if it is selected as the reference clock. For ATAO and AIS,
MCLK is always used as the reference clock.
Reference clock during Transmit All Ones (TAO) condition or send-
ing PRBS in hardware control mode.
Figure-17 shows the chip operation status in different conditions of
MCLK and TCLKn. The missing of MCLK will set all the TTIPn/TRINGn to
high impedance state.
3.10.2 TRANSMIT CLOCK (TCLK)
TCLKn is used to sample the transmit data on TDn/TDPn, TDNn. The
active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0, 04H...).
During Transmit All Ones or PRBS pattern, either TCLKn or MCLK can be
used as the reference clock. This is selected by the PATT_CLK bit
(MAINT0, 0CH...).
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0CH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0CH) is set to ‘1’.
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
bit (STAT0, 16H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
is not using MCLK to transmit internal patterns (TAOS, All Zeros and
PRBS). When TCLK is detected again, TCLK_LOS bit (STAT0, 16H...) will
be cleared. The reference frequency to detect a TCLK loss is derived from
MCLK.
Figure-17 TCLK Operation Flowchart
both the transmitters high
impedance
yes
MCLK=H/L?
normal operation
Clocked
TCLKn status?
L/H
clocked
generate transmit clock loss
interrupt if not masked in
software control mode;
transmitter n high impedance
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