參數(shù)資料
型號(hào)： IDT821068
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： OCTAL PROGRAMMABLE PCM CODEC
中文描述： 八路可編程PCM編解碼器
文件頁(yè)數(shù)： 29/45頁(yè)
文件大小： 589K
代理商： IDT821068
INDUSTRIAL TEMPERATURE RANGE
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
29
23. FSK Mark Length (37H/B7H), Read/Write
Mark Length bits (ML[7:0]) determine the number of mark bits ‘1’ which will be transmitted in initial flag phase. The value is valid from 0 to
255(d), the default value is 0(d). When 0(d) is selected, no mark signal will be sent.
24. FSK Start, Mark After Send, FSK Mode Select, FSK Channel Select and FSK On/Off (38H/B8H), Read/Write
FSK Start bit (FS) should be set to ‘1’ when users are going to send out FSK data. It will be cleared TO the default value ‘0’ at the end of word
data. When Seizure Length, Mark Length together with Data Length bits are all set to 0(d), the FSK Start bit will be reset to ‘0’ immediately after it
is set to ‘1’.
Mark After Send bit (MAS) determine the FSK block operation after the word data has been sent.
MAS = 0: The output will be muted after sending out word data (default);
MAS = 1: After sending out one frame of message data (=< 64 bytes), IDT821068 keeps sending a series of '1' until the MAS bit is set
to 0 and the FS bit is set to 1.
FSK Mode Select bit (FMS) determines which specification the IDT821068 follows:
FMS = 0: Bellcore specification is selected (default);
FMS = 1: BT specification is selected.
FSK Channel Select bits (FCS[2:0]) selects the channel on which FSK operation will be implemented.
FCS[2:0] = 000: Channel 1 is selected (default);
FCS[2:0] = 001: Channel 2 is selected;
FCS[2:0] = 010: Channel 3 is selected;
FCS[2:0] = 011: Channel 4 is selected;
FCS[2:0] = 100: Channel 5 is selected;
FCS[2:0] = 101: Channel 6 is selected;
FCS[2:0] = 110: Channel 7 is selected;
FCS[2:0] = 111: Channel 8 is selected.
FSK On/Off (FO) enables or disables the whole FSK function block.
FO = 0: FSK is disabled (default);
FO = 1: FSK is enabled.
25. Loop Control and PLL Power Down (3CH/BCH), Read/Write
Loop Control bits (LP[4:0]) determine the loopback status. Refer to Figure 9 for detail information.
LP[0] = 0: Analog Loopback via PCM Highway is disabled (default);
LP[0] = 1: Analog Loopback via PCM Highway is enabled;
LP[1] = 0: Digital Loopback via PCM Highway is disabled (default);
LP[1] = 1: Digital Loopback via PCM Highway is enabled;
LP[2] = 0: Digital Loopback via 8 kHz Interface is disabled (default);
LP[2] = 1: Digital Loopback via 8 kHz Interface is enabled;
LP[3] = 0: Analog Loopback via 8 kHz Interface is disabled (default);
LP[3] = 1: Analog Loopback via 8 kHz Interface is enabled;
LP[4] = 0: Digital Loopback via Analog Interface is disabled (default);
LP[4] = 1: Digital Loopback via Analog Interface is enabled.
PLL Power Down Bit (PLLPD) controls the status of Phase Lock Loop.
PLLPD = 0: the device is in normal operation (default);
PLLPD = 1: Phase Lock Loop is powered down. The device works in Power-Saving mode. All clocks stop running.
b7
R
/W
ML[7]
b6
0
b5
1
b4
1
b3
0
b2
1
b1
1
b0
1
Command
I/O data
ML[6]
ML[5]
ML[4]
ML[3]
ML[2]
ML[1]
ML[0]
b7
R
/W
FO
b6
0
b5
1
b4
1
b3
1
R
b2
0
FMS
b1
0
b0
0
FS
Command
I/O data
FCS[2]
FCS[1]
FCS[0]
MAS
b7
R
/W
R
b6
0
b5
1
R
b4
1
b3
1
b2
1
b1
0
b0
0
Command
I/O data
PLLPD
LP[4]
LP[3]
LP[2]
LP[1]
LP[0]
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