參數(shù)資料
型號(hào)： IDT821068
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： OCTAL PROGRAMMABLE PCM CODEC
中文描述： 八路可編程PCM編解碼器
文件頁(yè)數(shù)： 25/45頁(yè)
文件大?。?/td> 589K
代理商： IDT821068
INDUSTRIAL TEMPERATURE RANGE
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
25
CHCLK1_SEL[3:0] = 0101: CHCLK1 outputs digital signal at the frequency of 1000/10 Hz;
CHCLK1_SEL[3:0] = 0110: CHCLK1 outputs digital signal at the frequency of 1000/12 Hz;
CHCLK1_SEL[3:0] = 0111: CHCLK1 outputs digital signal at the frequency of 1000/14 Hz;
CHCLK1_SEL[3:0] = 1000: CHCLK1 outputs digital signal at the frequency of 1000/16 Hz;
CHCLK1_SEL[3:0] = 1001: CHCLK1 outputs digital signal at the frequency of 1000/18 Hz;
CHCLK1_SEL[3:0] = 1010: CHCLK1 outputs digital signal at the frequency of 1000/20 Hz;
CHCLK1_SEL[3:0] = 1011: CHCLK1 outputs digital signal at the frequency of 1000/22 Hz;
CHCLK1_SEL[3:0] = 1100: CHCLK1 outputs digital signal at the frequency of 1000/24 Hz;
CHCLK1_SEL[3:0] = 1101: CHCLK1 outputs digital signal at the frequency of 1000/26 Hz;
CHCLK1_SEL[3:0] = 1110: CHCLK1 outputs digital signal at the frequency of 1000/28 Hz;
CHCLK1_SEL[3:0] = 1111: CHCLK1 outputs 0 permanently.
CHCLK2_SEL bits configure the programmable output pin CHCLK2.
CHCLK2_SEL[1:0] = 00: CHCLK2 outputs 1 permanently (default);
CHCLK2_SEL[1:0] = 01: CHCLK2 outputs digital signal at the frequency of 512 kHz;
CHCLK2_SEL[1:0] = 10: CHCLK2 outputs digital signal at the frequency of 256 kHz;
CHCLK2_SEL[1:0] = 11: CHCLK2 outputs digital signal at the frequency of 16.384 MHz.
9. SLIC Debounced Input SI1 (28H), Read Only
SIA is the debounced version of SI1, see Figure 10 (Debounce filters) on Page 15. The SIA bits SIA[7:0] contain SLIC status which SLIC interface
pin SI1 receives.
SIA[0]: debounced data of SI1 on Channel 1 (default value is 0);
SIA[1]: debounced data of SI1 on Channel 2 (default value is 0);
SIA[2]: debounced data of SI1 on Channel 3 (default value is 0);
SIA[3]: debounced data of SI1 on Channel 4 (default value is 0);
SIA[4]: debounced data of SI1 on Channel 5 (default value is 0);
SIA[5]: debounced data of SI1 on Channel 6 (default value is 0);
SIA[6]: debounced data of SI1 on Channel 7 (default value is 0);
SIA[7]: debounced data of SI1 on Channel 8 (default value is 0).
10. SLIC Debounced Input SI2 (29H), Read Only
SIB is the debounced version of SI2, see Figure 10 (Debounce filters) on Page 15. The SIB bits SIB[7:0] contain SLIC ground key status which
SLIC interface pin SI2 receives.
SIB[0]: debounced data of SI2 on Channel 1 (default value is 0);
SIB[1]: debounced data of SI2 on Channel 2 (default value is 0);
SIB[2]: debounced data of SI2 on Channel 3 (default value is 0);
SIB[3]: debounced data of SI2 on Channel 4 (default value is 0);
SIB[4]: debounced data of SI2 on Channel 5 (default value is 0);
SIB[5]: debounced data of SI2 on Channel 6 (default value is 0);
SIB[6]: debounced data of SI2 on Channel 7 (default value is 0);
SIB[7]: debounced data of SI2 on Channel 8 (default value is 0).
11. SLIC Real-time SB1 Data (2AH/AAH), Read/Write
SB1 bits contain the information of SLIC bidirectional pin SB1.
SB1[0]: SB1 data on Channel 1 (default value is 0);
SB1[1]: SB1 data on Channel 2 (default value is 0);
b7
0
b6
0
b5
1
b4
0
b3
1
b2
0
b1
0
b0
0
Command
I/O data
SIA[7]
SIA[6]
SIA[5]
SIA[4]
SIA[3]
SIA[2]
SIA[1]
SIA[0]
b7
0
b6
0
b5
1
b4
0
b3
1
b2
0
b1
0
b0
1
Command
I/O data
SIB[7]
SIB[6]
SIB[5]
SIB[4]
SIB[3]
SIB[2]
SIB[1]
SIB[0]
b7
R
/W
SB1[7]
b6
0
b5
1
b4
0
b3
1
b2
0
b1
1
b0
0
Command
I/O data
SB1[6]
SB1[5]
SB1[4]
SB1[3]
SB1[2]
SB1[1]
SB1[0]
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