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參數(shù)資料
| 型號： | IDT821068 |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | Codec |
| 英文描述： | OCTAL PROGRAMMABLE PCM CODEC |
| 中文描述： | 八路可編程PCM編解碼器 |
| 文件頁數(shù)： | 14/45頁 |
| 文件大?。?/td> | 589K |
| 代理商： | IDT821068 |
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INDUSTRIAL TEMPERATURE RANGE
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
14
SLIC CONTROL
The SLIC interface of IDT821068 for each channel consists of 7
pins: 2 inputs SI1 and SI2, 2 I/O pins SB1 and SB2, together with 3
outputs SO1, SO2 and SO3.
SI1 AND SI2
In both MPI and GCI mode, SLIC inputs SI1 and SI2 can be read via
Global Command 9 or 10 for all 8 channels. The eight SIA bits of
Global Command 9 represent the eight debounced SI1 signals on
corresponding channels, while the eight SIB bits of Global Command
10 represent the eight debounced SI2 signals on corresponding
channels. In this way, information on SI1 or SI2 for eight channels can
be obtained from IDT821068 with a read operation. Both SI1 and SI2
can be assigned to off-hook, ring trip, ground key signals or other
signals. The 2 Global Commands allow the microprocessor a more
efficient way of obtaining time-critical data such as on/off-hook and ring
trip information.
In MPI operation, SI1 and SI2 data for each channel can also be
read by Local Command 9.
In GCI operation, SI1 and SI2 data for each channel can be
obtained in the field of upstream C/I octet. Refer to GCI Interface
Description.
SB1 AND SB2
In both MPI and GCI mode, SLIC I/O pin SB1 for each channel can
be configured as input or output separately (the default direction is
input), by Global Command 13. Each bit in this command
corresponds to one channel’s SB1 direction. When a bit in this
command is set to 0, the SB1 pin of its corresponding channel is
configured as an input; when the bit is set to 1, the SB1 pin of its
corresponding channel is configured as an output.
Global Command 14 determines the I/O direction of the SB2 pins
for each channel in the same way.
In MPI mode, if SB1 and SB2 are selected as inputs, they can be
read by Global Command 11 or 12, which provides SB1 or SB2
information for all 8 channels; or by Local Command 9, which
provides SB1 and SB2 information for each individual channel.
In MPI mode, if SB1 and SB2 are selected as outputs, data can be
written to them by Global Command 11 or 12 only.
In GCI mode, if SB1 and SB2 are selected as inputs, the information
of them can be read by Global Command 11 or 12. For SB1, the
information can also be read in the field of upstream C/I channel octet.
In GCI mode, if SB1 and SB2 are selected as outputs, data can only
be written to them through downstream C/I channel octet. Refer to GCI
Interface Description for detail.
SO1, SO2 AND SO3
SLIC output signals to SO1, SO2 and SO3 pins can only be written
for each individual channel.
In MPI mode, Local Command 9 writes the 3 output pins for each
channel. When Local Command 9 reads a channel’s SLIC pins, the
SO1-SO3 bits will be read out with the data written in at last write
operation.
In GCI mode, data can only be written to SO1, SO2 and SO3
through downstream C/I channel octet.
HARDWARE RING TRIP
In order to prevent the damage caused by high voltage ring signal,
the IDT821068 offers a hardware ring trip function to respond to the
off-hook signal as fast as possible. This function can be enabled by
setting RTE bit in Global Command 15.
The off-hook signal can be input via either SI1 or SI2, while the ring
control signal can be output via any pin of SO1, SO2, SO3, SB1 and
SB2 (when SB1 and SB2 are configured as outputs). In Global
Command 15, IS bit determines which input is used and OS[2:0] bits
determine which output is used.
When a valid off-hook signal arrives on SI1 or SI2, the IDT821068
will turn off the ring signal by inverting the selected output, regardless
of the value in corresponding SLIC output control register (the content
in the corresponding SLIC control register should be changed later).
This function provides a much faster response to off-hook signal than
the software ring trip which turns off the ring signal by changing the
value of selected output in the corresponding register.
The IPI bit in Global Command 15 is used to indicate the valid
polarity of input. If the off-hook signal is active low, the IPI bit should be
set to 0; if the off-hook signal is active high, the IPI bit should be set to
1.
The OPI bit in Global Command 15 is used to indicate the valid polarity
of output. If the ring control signal is required to be low in normal status
and be high to activate a ring, the OPI bit should be set to 1; if it is
required to be high in normal status and be low to activate a ring, the OPI
bit should be set to 0.
For example, in a system where the off-hook signal is active low
and ring control signal is active high, the IPI bit in Global Command 15
should be set to 0 and the OPI bit should be set to 1. In normal status,
the selected input (off-hook signal) is high and the selected output
(ring control signal) is low. When the ring is activated by setting the
output (ring control signal) high, a low pulse appearing on the input
(off-hook signal) will inform the device to invert the output to low and
cut off the ring signal.
INTERRUPT AND INTERRUPT ENABLE
An interrupt mechanism is offered in IDT821068 for reading the
SLIC input status. Each SLIC input generates interrupt respectively
when it changes state.
Any of SI1, SI2, SB1 and SB2 (when SB1 and SB2 are configured
as inputs) can be interrupt source. As SI1 and SI2 are debounced
signals while SB1 and SB2 are not, users should be careful if they
select SB1 and SB2 as interrupt sources.
The IDT821068 provides an Interrupt Enable Command (Local
Command 2) for each interrupt source to enable its interrupt ability.
This command contains 4 bits (IE[3:0]) for each channel. Each bit of
the IE[3:0] corresponds to one interrupt source of the specific channel.
The device will ignore the interrupt signal if its corresponding bit in
Interrupt Enable Command is set to 0 (disable).
Multiple interrupt sources can be enabled at the same time. The
interrupt sources can only be cleared by executing a read operation of
Local Command 9, by which clear all the 7 interrupt sources for the
corresponding channel.
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相關代理商/技術參數(shù) |
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