參數(shù)資料
型號： IDT821068
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： OCTAL PROGRAMMABLE PCM CODEC
中文描述： 八路可編程PCM編解碼器
文件頁數(shù)： 24/45頁
文件大?。?/td> 589K
代理商： IDT821068
INDUSTRIAL TEMPERATURE RANGE
IDT821068 OCTAL PROGRAMMABLE PCM CODEC
24
CE[1] = 0: Disabled, Channel 2 can not receive Local Commands and Coe-RAM Commands (default);
CE[1] = 1: Enabled, Channel 2 can receive Local Commands and Coe-RAM Commands.
CE[2] = 0: Disabled, Channel 3 can not receive Local Commands and Coe-RAM Commands (default);
CE[2] = 1: Enabled, Channel 3 can receive Local Commands and Coe-RAM Commands.
CE[3] = 0: Disabled, Channel 4 can not receive Local Commands and Coe-RAM Commands (default);
CE[3] = 1: Enabled, Channel 4 can receive Local Commands and Coe-RAM Commands.
CE[4] = 0: Disabled, Channel 5 can not receive Local Commands and Coe-RAM Commands (default);
CE[4] = 1: Enabled, Channel 5 can receive Local Commands and Coe-RAM Commands.
CE[5] = 0: Disabled, Channel 6 can not receive Local Commands and Coe-RAM Commands (default);
CE[5] = 1: Enabled, Channel 6 can receive Local Commands and Coe-RAM Commands.
CE[6] = 0: Disabled, Channel 7 can not receive Local Commands and Coe-RAM Commands (default);
CE[6] = 1: Enabled, Channel 7 can receive Local Commands and Coe-RAM Commands.
CE[7] = 0: Disabled, Channel 8 can not receive Local Commands and Coe-RAM Commands (default);
CE[7] = 1: Enabled, Channel 8 can receive Local Commands and Coe-RAM Commands.
7. PCM Data Offset, PCM Clock Slope, Data Mode Select, and A/
m
-Law Select (26H/A6H), Read/Write
PCM Data Offset bits (DO[2:0]) configure the number of clocks that PCM data transmit and receive time slot is offset from the Frame Synchro-
nous Signal (FS). (For MPI mode only)
DO[2:0] = 000: 0 BCLK period (default);
DO[2:0] = 001: 1 BCLK period;
DO[2:0] = 010: 2 BCLK periods;
DO[2:0] = 011: 3 BCLK periods;
DO[2:0] = 100: 4 BCLK periods;
DO[2:0] = 101: 5 BCLK periods;
DO[2:0] = 110: 6 BCLK periods;
DO[2:0] = 111: 7 BCLK periods.
PCM Clock Slope (CS[2:0]) bits select transmit and receive clock edge. (For MPI mode only)
CS[2] = 0: single clock (default);
CS[2] = 1: double clock;
CS[1:0] = 00: IDT821068 transmits data on rising edges of BCLK, and receives data on falling edges of BCLK (default);
CS[1:0] = 01: IDT821068 transmits data on rising edges of BCLK, and receives data on rising edges of BCLK;
CS[1:0] = 10: IDT821068 transmits data on falling edges of BCLK, and receives data on falling edges of BCLK;
CS[1:0] = 11: IDT821068 transmits data on falling edges of BCLK, and receives data on rising edges of BCLK.
Data Mode Select bit (DMS) defines the coding format of the voice data. (For both MPI and GCI mode)
DMS = 0: compressed code (default);
DMS = 1: linear code.
A/
μ
-law Select bit (LS) selects A-law or
μ
-law. (For both MPI and GCI mode)
LS = 0: A-law (default);
LS = 1:
μ
-law.
8. Chopper Clock Select (27H/A7H), Read/Write
CHCLK1_SEL bits configure the programmable output pin CHCLK1.
CHCLK1_SEL[3:0] = 0000: CHCLK1 outputs 1 permanently (default);
CHCLK1_SEL[3:0] = 0001: CHCLK1 outputs digital signal at the frequency of 1000/2 Hz;
CHCLK1_SEL[3:0] = 0010: CHCLK1 outputs digital signal at the frequency of 1000/4 Hz;
CHCLK1_SEL[3:0] = 0011: CHCLK1 outputs digital signal at the frequency of 1000/6 Hz;
CHCLK1_SEL[3:0] = 0100: CHCLK1 outputs digital signal at the frequency of 1000/8 Hz;
b7
R
/W
LS
b6
0
b5
1
b4
0
b3
0
b2
1
b1
1
b0
0
Command
I/O data
DMS
CS[2]
CS[1]
CS[0]
DO[2]
DO[1]
DO[0]
b7
R
/W
b6
0
b5
1
b4
0
b3
0
b2
1
b1
1
b0
1
Command
I/O data
R
R
CHCLK2_
SEL[1]
CHCLK2_
SEL[0]
CHCLK1_
SEL[3]
CHCLK1_
SEL[2]
CHCLK1_
SEL[1]
CHCLK1_
SEL[0]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT821068PX 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC
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