
32
INDUSTRIAL TEMPERATURE RANGE
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
APPENDIX: IDT821064 Coe-RAM Address Mapping
ACT RAM
ACR RAM
GTX RAM
GRX RAM
ACT RAM
ACR RAM
GTX RAM
GRX RAM
ACR RAM
GTX RAM
GRX RAM
IMF RAM
ECF RAM
TONE RAM
GIS RAM
ACT RAM
GRX RAM
FRR RAM
GTX RAM
FRX RAM
0
7
000
001
010
011
100
8
15
16
23
24
31
32
39
channel0
channel1
channel2
channel3
Word#
b[2:0] of a Coe-RAM
Command
Word #
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
Address
100
,111
100
,110
100
,101
100
,100
100
,011
100
,010
100
,001
100
,000
011
,111
011
,110
011
,101
011
,100
011
,011
011
,010
011
,001
011
,000
010
,111
010
,110
010
,101
010
,100
Function
GRX RAM
Word #
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
010
,011
010
,010
010
,001
010
,000
001
,111
001
,110
001
,101
001
,100
001
,011
001
,010
001
,001
001
,000
000
,111
000
,110
000
,101
000
,100
000
,011
000
,010
000
,001
000
,000
Function
GIS RAM
FRR RAM
GTX RAM
ECF RAM
FRX RAM
Amplitude Coefficient of Tone Generator 1
Frequency Coefficient of Tone Generator 1
Amplitude Coefficient of Tone Generator 0
Frequency Coefficient of Tone Generator 0
IMF RAM
Generally, 6 bits of address are needed to locate each word of the 40 Coe-RAM words. The 40 words of Coe-RAM are divided into 5 blocks with
8 words per block in IDT821064, so only 3 bits of address are needed to locate each of the block. When the address of a Coe-RAM block (b[2:0])
is specified in a Coe-RAM Command, all 8 words of this block will be addressed automatically, with the highest order word first ( IDT821064 will
count down from '111' to '000' so that it accesses the 8 words successively). Refer to page 16 and 17 for more information.
The address assignment for the 40 words Coe-RAM is shown in the following table. The number in the “Address” column is the actual hexadecimal
address of the Coe-RAM word, as the IDT821064 handles the lower 3 bits automatically, only the higher 3 bits (in bold style) are needed for a Coe-
RAM Command. It should be noted that, when addressing the GRX RAM, the FRR RAM will be addressed at the same time.
Table 7 - Coe-RAM Address Allocation