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參數(shù)資料
| 型號： | IDT821064 |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | Codec |
| 英文描述： | QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| 中文描述： | 四可編程PCM編解碼器GCI界面 |
| 文件頁數(shù)： | 12/33頁 |
| 文件大?。?/td> | 510K |
| 代理商： | IDT821064 |
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12
INDUSTRIAL TEMPERATURE RANGE
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
SLIC CONTROL
The SLIC interface of IDT821064 for each channel consists of 7 pins:
2 inputs SI1 and SI2, 3 I/O pins SB1, SB2 and SB3, together with 2
outputs SO1 and SO2.
SI1 AND SI2
SLIC inputs SI1 and SI2 can be read in 2 ways - via Global Command
7 or via the field of upstream C/I octet.
SI1 and SI2 data of all 4 channels can be read by executing a read
operation of Global Command 7. The SIA[3:0] bits of Global Command
7 represent the debounced SI1 signal of channel 4 to channel 1. The
SIB[3:0] bits of Global Command 7 represent the debounced SI2 signal
of channel 4 to channel 1.
Both SI1 and SI2 can be assigned to off-hook, ring trip, ground key
signals or other signals. The Global Command 7 provides for users a
more efficient way to obtain time-critical data such as on/off-hook and
ring trip information from the SLIC inputs SI1 and SI2.
SI1 and SI2 data for each channel can also be obtained in the upstream
C/I channel. See page 6 for details.
SB1, SB2 AND SB3
SLIC I/O pin SB1 for each channel can be configured as input or
output separately, by Global Command 8. The SB1C[3:0] bits of this
command correspond to the SB1 directions of channel 4 to channel 1:
‘0’ means input and '1' means output. Similarly, the SB2C[3:0] bits of
Global Command 9 determine the I/O direction of the SB2 pins for each
channel, and the SB3C[3:0] bits of Global Command 10 determine the
I/O direction of the SB3 pins for each channel.
When the SB1, SB2 or SB3 pin is selected as input, its information
can be read by Global Command. By executing a read operation of
Global Command 8, 9 or 10, users can obtain information of SB1, SB2
or SB3 respectively. The SB1[3:0] bits in Global Command 8, the SB2[3:0]
bits in Global Command 9 and the SB3[3:0] bits of Global Command 10
provide the SB1, SB2 and SB3 information respectively for all four
channels. For SB1, the information of it can also be read through
upstream C/I channel. But for SB2 and SB3, the information of them
only can be read by Global Command.
When SB1, SB2 and SB3 are configured as outputs, they can only be
written through the downstream C/I channel. Refer description of C/I
channel in page 6 for details.
SO1 AND SO2
SO1 and SO2 are two SLIC signaling outputs, data can only be written
to them through downstream C/I channel.
HARDWARE RING TRIP
In order to prevent the damage caused by high voltage ring signal,
the IDT821064 offers a hardware ring trip function to respond to the off-
hook signal as fast as possible. This function can be enabled by setting
RTE bit in Global Command 6.
The off-hook signal can be input via either SI1 or SI2, while the ring
control signal can be output via any pin of SO1, SO2, SB1, SB2 and SB3
(when SB1-SB3 configured as output). In Global Command 6, IS bit
determines which input is used and OS[2:0] bits determine which output
is used.
When a valid off-hook signal arrives on SI1 or SI2, the IDT821064 will
turn off the ring signal by inverting the selected output, regardless of the
value in corresponding SLIC output control register (the content in the
corresponding SLIC control register should be changed later). This
function provides a much faster response to off-hook signal than the
software ring trip which turns off the ring signal by changing the value of
selected output in the corresponding register.
The IPI bit in Global Command 6 is used to indicate the valid polarity
of input. If the off-hook signal is active low, the IPI should be set to ‘0’; if
the off-hook signal is active high, the IPI should be set to ‘1’.
The OPI bit in Global Command 6 is used to indicate the valid polarity of
output. If the ring control signal is required to be low in normal status and be
high to activate a ring, the OPI should be set to ‘1’; if it is required to be high
in normal status and be low to activate a ring, the OPI should be set to ‘0’.
For example, in a system where the off-hook signal is active low and
ring control signal is active high, the IPI in Global Command 6 should be
set to ‘0’ and the OPI bit should be set to ‘1’. In normal status, the selected
input (off-hook signal) is high and the selected output (ring control signal)
is low. When the ring is activated by setting the output (ring control signal)
high, a low pulse appearing on the input (off-hook signal) will inform the
device to invert the output to low and cut off the ring signal.
CHOPPER CLOCK
IDT821064 offers two programmable chopper clock outputs: CHCLK1
and CHCLK2. Both CHCLK1 and CHCLK2 are synchronous to MCLK.
CHCLK1 outputs signal with programmable 2-28 ms clock cycle, while
the frequency of CHCLK2 can be any of 256 kHz, 512 kHz and 16.384
MHz. The frequency selection of chopper clocks can be implemented
by Global Command 4. The chopper clocks can be used to drive the
power supply switching regulators on SLICs.
DEBOUNCE FILTERS
For each channel, IDT821064 provides two debounce filter circuits:
Debounced Switch Hook (DSH) Filter for SI1 and Ground Key (GK) Filter
for SI2 as shown in Figure 7. They are used to buffer the input signals on
SI1 and SI2 pins before changing the state of the SLIC Debounced Input
SI1/SI2 Register (Global Command 7). Frame Sync (FS) is necessary
for both DSH filter and GK filter.
DSH Debounce bits in Local Command 3 can program the debounce
time of SI1 input from SLIC on individual channel. The DSH filter is initially
clocked at half of the frame sync rate (250
μ
s), and any data changing at
this sample rate resets a programmable counter. The counter clocks at
the rate of 2 ms, and the value of the counter can be varied from 0 to 30
which is determined by Local Command 3. The corresponding SIA bit in
the SLIC Debounced Input SI1 Register (accessed by Global Command
7) would not be updated until the value of the counter is reached. SI1 bit
usually contains SLIC switch hook status.
GK Debounce bits in Local Command 3 can program the debounce
interval of SI2 input from SLIC on corresponding channel. The debounced
signal will be output to SIB of SLIC Debounced Input SI2 Register
(accessed by Global Command 7). The GK debounce filter consists of
an up/down counter that ranges between 0 and 6. This six-state counter
is clocked by the GK timer at the sampling period of 0-30 ms, as
programmed by Local Command 3. When the sampled value is low,
the counter is decremented by each clock pulse. When the sampled
value is high, the counter is incremented by each clock pulse. When the
counter increments to 6, it sets a latch whose output is routed to the
corresponding SIB bit. If the counter decrements to 0, this latch is cleared
相關PDF資料 |
PDF描述 |
|---|---|
| IDT821064PQF | QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821068 | OCTAL PROGRAMMABLE PCM CODEC |
| IDT821068PX | OCTAL PROGRAMMABLE PCM CODEC |
| IDT821621 | LONG HAUL SLIC |
| IDT821621J | LONG HAUL SLIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT821064PQF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821068 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
| IDT821068PX | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
| IDT821621 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LONG HAUL SLIC |
| IDT821621J | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LONG HAUL SLIC |
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