參數(shù)資料
型號(hào)： IDT821064
廠商： Integrated Device Technology, Inc.
元件分類(lèi)： Codec
英文描述： QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
中文描述： 四可編程PCM編解碼器GCI界面
文件頁(yè)數(shù)： 16/33頁(yè)
文件大?。?/td> 510K
代理商： IDT821064
16
INDUSTRIAL TEMPERATURE RANGE
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
b7
b6
b 5
b 4
b3
b2
b1
b0
1
0
0
A
/B
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OPERATING THE IDT821064
PROGRAMMING DESCRIPTION
PROGRAM START BYTE
The IDT821064 uses the monitor channel for the exchange of status
or mode information with high level processors. The messages
transmitted in the monitor channel have different data structures. For a
complete command operation, the first byte of monitor channel data
indicates the address of the device either sending or receiving the data.
All monitor channel messages to/from IDT821064 begin with the following
Program Start (PS) byte:
Because one monitor channel is shared by two voice data channels
to transmit maintenance information, so an
A
/B bit is used in the PS
byte to identify the two channels. For easy description, we name them
as Channel A and Channel B. Herein,
A
/B = 0: means that Channel A is the source (upstream) or destination
(downstream) - 81H;
A
/B = 1: means that Channel B is the source (upstream) or destination
(downstream) - 91H.
The Program Start byte is followed by a command (global/local register
command or RAM command) byte. For Global Command, the
A
/B bit
in the PS byte can be ignored. If the command byte specifies a write,
then from 1 to 16 additional data bytes may follow (1-4 for registers, 1-
16 for RAM). If the command byte specifies a read, additional data bytes
may follow. IDT821064 responds to the read command by sending up
to 16 data bytes upstream containing the information requested by the
upstream controller. Each byte on monitor channel must be transferred
at least twice and in two consecutive frames.
IDENTIFICATION COMMAND
In order to distinguish different devices unambiguously by software, a
two byte identification command is defined for analog lines GCI devices
(8000H):
Each device will then respond with its specific identification code. For
IDT821064, this two byte identification code is (8082H):
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
REGISTER COMMAND AND RAM COMMAND
There are three types of commands used in monitor channel to
accessing registers and RAM, they are:
Local Command (LC), which is used to configure each channel by
reading/writing the Local Registers, there are 5 Local Registers per
channel available;
Global Command (GC), which is used to configure all 4 channels by
reading/writing the Global Registers, there are totally 21 Global Registers
shared by the 4 channels;
RAM Command ( RC), which is used to read/write Coe-RAM and
FSK-RAM, there are 40 words (divided into 5 blocks) with 14 bits per
word Coe-RAM for each channel, and 32 words (divided into 4 blocks)
with 16 bits per word FSK-RAM shared by four channels. When a RC is
executed, 8 words of RAM (14 or 16 bits/word) will be accessed.
Register/RAM Command Format
The format of register command and RAM command is as the
following:
b7 b6 b5 b4 b3 b2 b1 b0
R
/W CT Address
R
/W: Read/Write Command bit.
b7 = 0: Read Command
b7 = 1: Write Command
CT: Command Type
b6 b5 = 00: LC - Local Command
b6 b5 = 01: GC - Global Command
b6 b5 = 10: Not Allowed
b6 b5 = 11: RC - RAM Command
Address: Specify which register or which block of RAM will be read or
written.
For both Local Command and Global Command, b[4:0] are used to
address the Local Registers or Global Registers.
For RAM Command, b4 is used to distinguish the Coe-RAM and the
FSK RAM:
b4 = 0: The RAM Command is for Coe-RAM
b4 = 1: The RAM Command is for FSK-RAM
When the RAM Command is for Coe-RAM, b[3:0] are used to address
the blocks of the Coe-RAM. When the RAM Command is for FSK-
RAM, b3 is always ‘0’ and b[2:0] are used to address the blocks of the
FSK-RAM.
Addressing Local Register
When addressing Local Registers, both the location of time slot
(determined by S1 and S0 pin) and the b4 bit in Program Start Byte
would indicate which channel to be addressed.
IDT821064 provides a Consecutive Adjacent Addressing for Read/
Write Local Registers. If the address for Local Register is specified in a
Local Command, then, according to the value of ‘b1b0’ of the address,
there will be 1 to 4 adjacent local registers will be read/write automatically
with the highest order first. For example, if the address of the register
specified by the Local Command is end with ‘11’ (b1b0=‘11’ ), 4 adjacent
registers will be Read/Write by this Command. If b1b0 =‘10’ , then 3
adjacent registers will be Read/Write. If b1b0 = ‘01’, then only 2 adjacent
registers will be Read/Write. If b1b0 = ‘00’, then only this specified register
will be Read/Write. The details of the Consecutive Adjacent Addressing
is shown in Table 4.
The Consecutive Adjacent Addressing can not be stopped once a
command is initiated. For write command, the number of bytes following
the command
must be the same as the number of registers being
written.
The transmission sequence of Local Command is shown in Table 5.
Addressing Global Register
The address of the 21 Global Registers is : 00000 - 10101 and 10111.
For the consecutive address, IDT821064 also provides a Consecutive
Adjacent Addressing for Read/Write, which is exactly the same as the
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IDT821621J 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:LONG HAUL SLIC
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