
21
INDUSTRIAL TEMPERATURE RANGE
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
b7
R
/W
SL[7]
b6
0
SL[6]
b5
1
SL[5]
b4
0
SL[4]
b3
1
SL[3]
b2
1
SL[2]
b1
1
SL[1]
b0
0
SL[0]
Command
I/O data
SLIC SB2 direction control bits (SB2C[3:0]) configure the direction of SLIC bidirectional interface pin SB2.
SB2C[0]=0: SB2 pin of channel 1 is configured as input (default);
SB2C[0]=1: SB2 pin of channel 1 is configured as output;
SB2C[1]=0: SB2 pin of channel 2 is configured as input (default);
SB2C[1]=1: SB2 pin of channel 2 is configured as output;
SB2C[2]=0: SB2 pin of channel 3 is configured as input (default);
SB2C[2]=1: SB2 pin of channel 3 is configured as output;
SB2C[3]=0: SB2 pin of channel 4 is configured as input (default);
SB2C[3]=1: SB2 pin of channel 4 is configured as output.
When SB2 pin of one channel is configured as input, the corresponding SB2 bit of this command contains the SB2 information of this channel;
When SB2 pin of one channel is configured as output, the corresponding SB2 bit of this command is reserved, data can only be written to the SB2
pin of the corresponding channel via GCI C/I octet.
10. SB3 Direction Control, SB1 Data (2BH/ABH), Read/Write
SLIC SB3 direction control bits (SB3C[3:0]) configure the direction of SLIC bidirectional interface pin SB3.
SB3C[0]=0: SB3 pin of channel 1 is configured as input (default);
SB3C[0]=1: SB3 pin of channel 1 is configured as output;
SB3C[1]=0: SB3 pin of channel 2 is configured as input (default);
SB3C[1]=1: SB3 pin of channel 2 is configured as output;
SB3C[2]=0: SB3 pin of channel 3 is configured as input (default);
SB3C[2]=1: SB3 pin of channel 3 is configured as output;
SB3C[3]=0: SB3 pin of channel 4 is configured as input (default);
SB3C[3]=1: SB3 pin of channel 4 is configured as output.
When SB3 pin of one channel is configured as input, the corresponding SB3 bit of this command contains the SB3 information of this channel;
When SB3 pin of one channel is configured as output, the corresponding SB3 bit of this command is reserved, data can only be written to the SB3
pin of the corresponding channel via GCI C/I octet.
11. FSK Flag Length (2CH/ACH), Read/Write
Flag Length bits (FL[7:0]) determine the number of flag bits ‘1’ which will be transmitted between the transmission of message bytes. The value
is valid from 0 to 255(d). The default value is 0(d). If 0(d) is selected, no flag signal will be sent.
12. FSK Data Length (2DH/ADH), Read/Write
Data Length bits (WL[7:0]) determine the number of all the data bytes which will be transmitted except flag. The value is valid from 0 to 64(d). Any
value larger than 64(d) will be taken as 64(d) by the CPU.
The default value of this register is 0(d). When 0(d) is selected, none of the word data will be sent out. When Mark After Send (MAS bit in Global
Command 15) is set to ‘1’, the mark signal will be sent; while Mark After Send is set to ‘0’, the transmission of mark signal will be terminated.
13. FSK Seizure Length (2EH/AEH), Read/Write
Seizure Length bits (SL[7:0]) determine the number of ‘01’ pairs which represent seizure phase( Seizure Length is two times of the value in
SL[7:0], which is valid from 0 to 255(d), corresponding to Seizure Length 0 to 510). The default value is 0(d). When 0(d) is selected, no seizure
signal will be sent.
b7
R
/W
SB3C[3]
b6
0
b5
1
b4
0
b3
1
b2
0
b1
1
b0
1
Command
I/O data
SB3C[2]
SB3C[1]
SB3C[0]
SB3[3]
SB3[2]
SB3[1]
SB3[0]
b7
R
/W
FL[7]
b6
0
b5
1
b4
0
b3
1
b2
1
b1
0
b0
0
Command
I/O data
FL[6]
FL[5]
FL[4]
FL[3]
FL[2]
FL[1]
FL[0]
b7
R
/W
WL[7]
b6
0
b5
1
b4
0
b3
1
b2
1
b1
0
b0
1
Command
I/O data
WL[6]
WL[5]
WL[4]
WL[3]
WL[2]
WL[1]
WL[0]