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參數(shù)資料
| 型號： | IDT821064 |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | Codec |
| 英文描述： | QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| 中文描述： | 四可編程PCM編解碼器GCI界面 |
| 文件頁數(shù)： | 17/33頁 |
| 文件大?。?/td> | 510K |
| 代理商： | IDT821064 |
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17
INDUSTRIAL TEMPERATURE RANGE
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
Address Specified by Local
Command
b4 b3 b2 b1 b0
X X X 1 1
(b1b0 = 11, 4 bytes DATA)
In/Out Data
Registers being
R
/W
Byte 1
Byte 2
Byte 3
Byte 4
X X X 11
X X X 10
X X X 01
X X X 00
X X X 1 0
(b1b0 = 10, 3 bytes DATA)
Byte 1
Byte 2
Byte 3
X X X 10
X X X 01
X X X 00
X X X 0 1
(b1b0 = 01, 2 bytes DATA)
Byte 1
Byte 2
X X X 01
X X X 00
X X X 0 0
(b1b0 = 00, 1 byte DATA)
Byte 1
X X X 00
GCI Monitor Channel
Downstream Upstream
Program Start byte (81H/91H)
Local/Global Command byte, write
Data byte 1
.
.
.
Data byte m*
Program Start byte (81H/91H)
Local/Global Command byte, read
Program Start byte (81H/91H)
Data byte 1
.
.
.
Data byte m*
Table 4 - Consecutive Adjacent Addressing
Table 5 - Local/Global Command Transmission Sequence
Local Registers. The procedure of Consecutive Adjacent Addressing
also can not be
stopped once a Global Command is initiated.
The transmission sequence of Global Command is shown in Table 5.
Refer to APPENDIX (Coe-RAM Mapping) for further details.
Each word in Coe-RAM is 14-bit wide. To write a Coe-RAM word, 16
bits (or, two 8-bit bytes) are needed to fulfill one word
with MSB first
,
but
the last two bits (LSB) will be neglected. When read, each Coe-RAM
word will output 16 bits with MSB first, but the last two bits are meaningless.
When addressing Coe-RAM, both the location of time slot (determined
by S1 and S0 pin) and the b4 bit in Program Start Byte would indicate
which channel to be addressed.
When the address of a Coe-RAM block is specified in a RAM
Command, all 8 words of this block will be Read/Write automatically,
with the highest order word first.
Only b[3:0] of a Coe-RAM Command can be used to address the 5
blocks in Coe-RAM, as b4 is used to distinguish the Coe-RAM and FSK-
RAM.
The transmission sequence of the Coe-RAM command is shown in
Table 6.
Table 6 - Coe-RAM/FSK-RAM Command Transmission Sequence
GCI Monitor Channel
Downstream Upstream
Program Start byte (81H/91H)
RAM Command byte, write
Data byte 1(Data_H of Word1)
Data byte 2(Data_L** of Word1)
Data byte 3(Data_H of Word2)
Data byte 4(Data_L of Word2)
.
.
.
Data byte 15(Data_H of Word8)
Data byte 16(Data_L of Word8)
Program Start byte (81H/91H)
RAM Command byte, read
Program Start byte (81H/91H)
Data byte 1(Data_H of Word1)
Data byte 2(Data_L** of Word1)
Data byte 3(Data_H of Word2)
Data byte 4(Data_L of Word2)
.
.
.
Data byte 15(Data_H of Word8)
Data byte 16(Data_L of Word8)
Addressing Coe-RAM
The Coe-RAM (Coefficient RAM) is consisted of 5 blocks for per
channel and totally 40 words. Each block contains 8 words. The 5 blocks
are:
- IMF RAM (Word 0 - Word 7), for Impedance Matching Filter
coefficient;
- ECF RAM (Word 8 - Word 15), for Echo Cancellation Filter coefficient;
- GIS RAM (Word 16 - Word 19) and Tone Generator RAM (Word 20
- Word 23), for Gain of Impedance Scaling and amplitude or frequency
for Tone Generator ;
- FRX RAM (Word 24 - Word 30) and GTX RAM (Word 31), for
Frequency Response Correction in Transmit Path coefficient and Gain
in Transmit Path;
- FRR RAM (Word 32 - Word 38) and GRX RAM (Word 39), for
Frequency Response Correction in Receive Path coefficient and Gain in
Receive Path.
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| IDT821064PQF | QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IDT821064PQF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE |
| IDT821068 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
| IDT821068PX | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:OCTAL PROGRAMMABLE PCM CODEC |
| IDT821621 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LONG HAUL SLIC |
| IDT821621J | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LONG HAUL SLIC |
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