![](http://datasheet.mmic.net.cn/330000/IDT821064_datasheet_16415949/IDT821064_3.png)
3
INDUSTRIAL TEMPERATURE RANGE
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
PIN DESCRIPTION
Name
Type
GNDA1
GNDA2
GNDA3
GNDA4
Pin Number
50
54
59
63
Description
P
Analog Ground.
All ground pins should be connected together.
GNDD
P
21
Digital Ground.
All digital signals are referred to this pin.
+5V Analog Power Supply.
These pins should be connected to ground via a 0.1
μ
F capacitor. All power supply pins should be connected
together.
+5V Digital Power Supply.
+5V Analog Power Supply.
This pin should be connected to ground via a 0.1
μ
F capacitor. All power supply pins should be connected
together.
Capacitor Noise Filter
This pin should be connected to ground via a 0.22
μ
F capacitor.
Analog Voice Inputs.
These pins should be connected to the SLIC via a capacitor (0.22
μ
F).
Voice Frequency Receiver Outputs.
These pins can drive 300
AC load. They can drive transformers directly.
VDDA12
VDDA34
VDDD
P
52
61
24
P
VDDB
P
57
CNF
-
56
VIN1-4
I
49, 55, 58, 64
VOUT1-4
O
51, 53, 60, 62
SI1_(1-4)
SI2_(1-4)
SB1_(1-4)
I
36, 47, 2, 13
35, 48, 1, 14
39, 44, 5, 10
SLIC signalling Inputs with debounced function for Channel 1-4.
SB2_(1-4)
SB3_(1-4)
SO1_(1-4)
SO2_(1-4)
I/O
38, 45, 4, 11
37, 46, 3, 12
41, 42, 7, 8
Bi-directional SLIC Signalling I/Os for Channel 1-4, can be programmed as Input or Output.
O
40, 43, 6, 9
SLIC Signalling Outputs for Channel 1-4.
DU
O
26
GCI Data Upstream
GCI data is serially transmitted to this pin for all 4 channels of IDT821064.
GCI Data Downstream
GCI data is received serially from this pin for all 4 channels of IDT821064.
Frame Sync.
FSC is an 8 kHz signal that identifies the beginning of Timeslot 0 in the GCI frame.
Data Clock.
The data clock is either 2.048 MHz or 4.096 MHz, which is determined automatically by IDT821064.
Time Slot Select
These pins are used to select one of the four time slot positions for Voice channels, Monitor and C/I channels.
Master Clock Input.
Master clock provides the clock for DSP. It can be 2.048 MHz or 4.096 MHz, which is determined automatically by
IDT821064. It is recommended to connect MCLK pin and DCL pin together.
Reset Input.
Forces the device to default state. Active low.
Chopper Clock Output.
Provides a programmable (2 -28 ms) output signal synchronous to MCLK.
Chopper Clock Output.
Provides a programmable 256 kHz, or 512 kHz or 16.384 MHz output signal synchronous to MCLK
Recommend to be connected to GNDD.
No connection
DD
I
27
FSC
I
31
DCL
I
32
S0
S1
I
18
19
MCLK
I
22
RESET
I
23
CHCLK1
O
33
CHCLK2
O
16
NCR
17,30
15,20,25
28,29,34
NC