參數(shù)資料
型號(hào)： IDT821064
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
中文描述： 四可編程PCM編解碼器GCI界面
文件頁(yè)數(shù)： 19/33頁(yè)
文件大?。?/td> 510K
代理商： IDT821064
19
INDUSTRIAL TEMPERATURE RANGE
IDT821064 QUAD PROGRAMMABLE PCM CODEC WITH GCI INTERFACE
COMMANDS LIST
Notes: 1.
R
/W = 0: Read ;
2.
‘R’
means Reserved for future use. This bit will always be filled in ‘ 0 ‘ in Write-Command, and be ignored in Read-command.
R
/W = 1: Write
GLOBAL COMMANDS:
1. Version Number (20H)/No Operation (A0H), Read/Write
By executing this read-command (20H), users can read out the version number of the IDT821064. The default value is 01H.
When executing the no operation command (A0H), a data byte (FFH) must follow to ensure proper operation.
2. Software Reset (A2H), Write Only
This command resets all Local Registers, but does not reset Global Registers and RAM. When executing this command, a data byte (FFH) must
follow to ensure proper operation.
3. Hardware Reset (A3H), Write Only
The action of this command is equivalent to pulling the
RESET
pin to low (Refer to page 18 for information about
RESET
operation). When
executing this command, a data byte (FFH) must follow to ensure proper operation.
4. Chopper Clock Select (24H/A4H), Read/Write
This command is used to determine the CHclk2 and CHclk1 output signals, the frequency is shown below:
CHclk2[1:0]=00: chclk2 outputs 1 permanently (default);
CHclk2[1:0]=01: chclk2 outputs digital signal at the frequency of 512 kHz;
CHclk2[1:0]=10: chclk2 outputs digital signal at the frequency of 256 kHz;
CHclk2[1:0]=11: chclk2 outputs digital signal at the frequency of 16384 kHz;
CHclk1[3:0]=0000: chclk1 outputs 1 permanently (default);
CHclk1[3:0]=0001: chclk1 outputs digital signal at the frequency of 1000/2 Hz;
CHclk1[3:0]=0010: chclk1 outputs digital signal at the frequency of 1000/4 Hz;
CHclk1[3:0]=0011: at the frequency of 1000/6 Hz;
CHclk1[3:0]=0100: at the frequency of 1000/8 Hz;
CHclk1[3:0]=0101: at the frequency of 1000/10 Hz;
CHclk1[3:0]=0110: at the frequency of 1000/12 Hz;
CHclk1[3:0]=0111: at the frequency of 1000/14 Hz;
CHclk1[3:0]=1000: at the frequency of 1000/16 Hz;
CHclk1[3:0]=1001: at the frequency of 1000/18 Hz;
CHclk1[3:0]=1010: at the frequency of 1000/20 Hz;
CHclk1[3:0]=1011: at the frequency of 1000/22 Hz;
CHclk1[3:0]=1100: at the frequency of 1000/24 Hz;
CHclk1[3:0]=1101: at the frequency of 1000/26 Hz;
CHclk1[3:0]=1110: at the frequency of 1000/28 Hz;
CHclk1[3:0]=1111: chclk1 outputs 0 permanently.
5. A/
m
-law, Linear/Compressed Code Selection (26H/A6), Read/Write
b7
Command
R
/W
I/O data
A-
μ
A/
μ
-law select bit (A-
μ
) selects the companding law:
A-
μ
= 0: A-law is selected (default)
A-
μ
= 1:
μ
-law is selected.
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
1
b0
0
Command
b7
1
b6
0
b5
1
b4
0
b3
0
b2
0
b1
1
b0
1
Command
b7
R
/W
b6
0
b5
1
b4
0
b3
0
b2
1
b1
0
b0
0
Command
I/O data
R
R
CHclk2
[1]
CHclk2
[0]
CHclk1
[3]
CHclk1
[2]
CHclk1
[1]
CHclk1
[0]
b7
R
/W
0
b6
0
0
b5
1
0
b4
0
0
b3
0
0
b2
0
0
b1
0
0
b0
0
1
Command
I/O Data
b6
0
VDS
b5
1
R
b4
0
R
b3
0
R
b2
1
R
b1
1
R
b0
0
R
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