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參數(shù)資料
| 型號(hào)： | IDT707288L20PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM, TQFP-100 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 125K |
| 代理商： | IDT707288L20PF8 |
6.42
IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
2
NO
T RECOMMENDED
FOR
NEW
DESIGNS
Description
The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-Switchable
Dual-PortedSRAMorganizedintofourindependent16Kx16banks.The
device has two independent ports with separate control, address, and
I/O pins for each port, allowing each port to asynchronously access
any 16K x 16 memory block not already accessed by the other port.
Accessesbytheportsintospecificbanksarecontrolledviabankselectpin
inputs under the user's control. Mailboxes are provided to allow inter-
processor communication. Interrupts are provided to indicate mailbox
writes have occurred. An automatic power down feature controlled by
the chip enables (
CE0andCE1)permitstheon-chipcircuitryofeachport
to enter a very low standby power mode and allows fast depth expansion.
TheIDT707288offersamaximumaddress-to-dataaccesstimeasfast
as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP).
Functionality
The IDT707288 is a high-speed asynchronous 64K x 16 Bank-
Switchable Dual-Ported SRAM, organized in four 16K x 16 banks. The
two ports are permitted independent, simultaneous access into separate
bankswithinthesharedarray.Therearefouruser-controlledBankSelect
input pins, and each of these pins is associated with a specific bank within
the memory array. Access to a specific bank is gained by placing the
associated Bank Select pin in the appropriate state: VIH assigns the bank
to the left port, and VIL assigns the bank to the right port (See Truth Table
IV). Once a bank is assigned to a particular port, the port has full access
to read and write within that bank. Each port can be assigned as many
banks within the array as needed, up to and including all four banks.
The IDT707288 provides mailboxes to allow inter-processor commu-
nication. Each port has four 16-bit mailbox registers available to which it
can write and read and which the opposite port can read only. These
mailboxes are external to the common SRAM array, and are accessed
by setting
MBSEL = VIL while setting CE = VIH. Each mailbox has an
associated interrupt: a port can generate an interrupt to the opposite port
by writing to the upper byte of any one of its four 16-bit mailboxes. The
interruptedportcancleartheinterruptbyreadingtheupperbyte.Thisread
will not alter the contents of the mailbox.
If desired, any source of interrupt can be independently masked via
software.Tworegistersareprovidedtopermitinterpretationofinterrupts:
the Interrupt Cause Register and the Interrupt Status Register. The
Interrupt Cause Register gives the user a snapshot of what has caused
the interrupt to be generated - the specific mailbox written to. The
information in this register provides post-mask signals: interrupt sources
that have been masked will not be updated. The Interrupt Status Register
givestheuserthestatusofallbitsthatcouldpotentiallycause aninterrupt
regardless of whether they have been masked. Truth Table V gives a
detailed explanation of the use of these registers.
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