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參數(shù)資料
| 型號： | IDT707288L20PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM, TQFP-100 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 125K |
| 代理商： | IDT707288L20PF8 |
6.42
IDT707288S/L
High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
12
NO
T RECOMMENDED
FOR
NEW
DESIGNS
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
NOTES:
1. R/
W or CE or UB and LB = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a
CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of
CE or R/W (or MBSEL or R/W) going to VIH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or MBSEL = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If
OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If
OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access RAM,
CE = VIL and MBSEL = VIH. To access mailboxes, CE = VIH and MBSEL = VIL. tEW must be met for either condition.
10. Refer to Truth Table I.
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
R/
W
tWC
tHZ
tAW
tWR
tAS
tWP
DATAOUT
(2)
tWZ
tDW
tDH
tOW
OE
ADDRESS
DATAIN
(6)
(4)
(7)
UB or LB
3592 drw 08
(9)
CE or
MBSEL
(9,10)
(7)
(3)
tLZ
VALID
(4)
3592 drw 09
tWC
tAS
tWR
tDW
tDH
ADDRESS
DATAIN
R/
W
tAW
tEW
UB or LB
(3)
(2)
(6)
CE or MBSEL
(9,10)
(9)
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