MODE3 - I2
參數(shù)資料
型號(hào)： IDT5V9885TNLGI
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 7/39頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN PLL 500MHZ 28VFQFPN
標(biāo)準(zhǔn)包裝： 490
類型： *
PLL： 帶旁路
輸入： LVCMOS，LVTTL
輸出： LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 500MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 28-VFQFPN（6x6）
包裝： 托盤
其它名稱： 800-2580
15
INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
MODE3 - I2C Programming Mode
Inthismode,GIN0,GIN1,GIN3andGIN5becomeSDAT(I2Cdata),SCLK(I2Cclock),SUSPENDandCLK_SELsignalpins,respectively.TheoutputGOUT0
will become an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock (LOSS_CLKIN). GIN2 and GIN4
are not available to users.
To enter this mode, I2C/JTAG pin must be set HIGH.
MODE4 - JTAG Programming Mode
In this mode, GIN0, GIN1, GIN2, GIN3, GIN4 and GIN5 will become TDI (JTAG data in), TCK (JTAG clock), TMS (JTAG control signal), SUSPEND, TRST
(JTAG reset) and CLK_SEL signal pins, respectively. The output GOUT0 will become JTAG TDO signal, and GOUT1 will be an indicator for loss of the selected
clock (LOSS_CLKIN).
To enter this mode, I2C/JTAG pin must be set LOW.
MODE2 - Manual Frequency Control (MFC=0) Mode for all PLLs
Inthismode,theconfigurationofPLL0,PLL1,andPLL2canbechangedduringoperation. TheGINxpinsareusedtocontroltheselectionofuptofourdifferent
Dx, Mx, RZx, CZx, CPx, and IPx configurations for each PLL. GIN0 and GIN1 become configuration selection pins for D0 and M0 of PLL0, GIN2 and GIN3
become configuration selection pins for PLL1, and GIN4 and GIN5 become configuration selection pins for D2 and M2 of PLL2. The output GOUT0 will become
an indicator for loss of PLL lock (LOSS_LOCK). GOUT1 pin will become an indicator for loss of the primary clock (LOSS_CLKIN).
The output banks will have two different P configurations to choose from for each of the four PLL configurations. Each of the two P configurations has its own
set of PM bits (See the PRE-SCALERS, FEEDBACK-DIVIDERS, POST-DIVIDERS section for more detail on the PM bits). Use the ODIV bit to choose which
post-dividerconfigurationtoassociatewithaspecificPLLconfiguration. Forexample,ifODIV2_CONFIG2=1,thenwhenConfig2isselectedQx[9:0]_CONFIG1
is selected as the post-divider value to be used. Note that there is an ODIVx bit for each of the PLL configurations. In this way, the post-divider values can change
withtheconfiguration.
To enter this mode, users must set MFC bit to "0", and I2C/JTAG pin must be left floating.
GIN1 Pin
GIN0 Pin
PLL0 Configuration Selection (Mode 2)
0
Configuration0
0
1
Configuration1
1
0
Configuration2
1
Configuration3
GIN3 Pin
GIN2 Pin
PLL1 Configuration Selection (Mode 2)
0
Configuration0
0
1
Configuration1
1
0
Configuration2
1
Configuration3
GIN5 Pin
GIN4 Pin
PLL2 Configuration Selection (Mode 2)
0
Configuration0
0
1
Configuration1
1
0
Configuration2
1
Configuration3
Manual Frequency Control modes
Multi-Purpose pins
Mode1
Mode2
JTAG
I2C
GIN0
TDI
SDAT
GIN1
TCK
SCLK
GIN2
TMS
n/a
GIN3
SUSPEND
GIN3
SUSPEND
GIN4
n/a
GIN4
TRST
n/a
GIN5
CLK_SEL
GIN5(1)
CLK_SEL
GOUT0
LOSS_LOCK
TDO
LOSS_LOCK
GOUT1
LOSS_CLKIN
NOTE:
1.
The PLL(s) will lock onto the primary clock and the manual switchover can be controlled by the PRIMCLK bit.
相關(guān)PDF資料
PDF描述
X9251TS24Z-2.7 IC XDCP QUAD 256TAP 100K 24-SOIC
X9268US24IZ IC XDCP DUAL 256TAP 50K 24-SOIC
X9268TS24IZ IC XDCP DUAL 256TAP 100K 24-SOIC
ICS87949AYILF IC CLK GENERATOR /1 /2 52-LQFP
VI-26V-MW CONVERTER MOD DC/DC 5.8V 100W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT5V9885TNLGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN
IDT5V9885TPFGI 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
IDT5V9885TPFGI8 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP
IDT5V9888NLGI 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
IDT5V9888NLGI8 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*