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參數(shù)資料
| 型號： | IDT5V9885TNLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-VFQFPN（6x6） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2580 |
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INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
POWER UP AND POWER SAVING FEATURES
If a global shutdown is enabled, SHUTDOWN pin asserted, most of the chip except for the PLLs will be powered down. In order to have a complete
power down of the chip, the PLLs must be powered down via the SUSPEND function or by setting the pre-scaler bits to '0x00' and disable the internal
GINx signals via the enable bits at memory address 0x05. Note that the register bits will not lose their state in the event of a chip power-down. The only
possibility that the register bits will lose their state is if the part was power-cycled. After coming out of shutdown mode, the PLLs will require time to relock.
During power up, the values of GIN4, GIN3, GIN2, GIN1 and GIN0 will be latched and used for PLL configuration selection, regardless of the state of the
I2C/JTAG pin and GINx being disabled via the GINENx bits. GIN5 will have an internal state of LOW. The GIN pins should be held LOW during power up
to select configuration0 as default. The output levels will be at an undefined state during power up.
The post-divider should never be disabled via PM bits after power up, or else it will render the output bank completely non-functional during normal
operation, (unless the output bank itself will not be used at all).
During power up, the VDD ramp must be monotonic.
LOSS OF LOCK AND INPUT CLOCK
The device employs a loss of lock and loss of input clock detection circuitry. The GOUT0/LOSS_LOCK and GOUT1/LOSS_CLKIN are the outputs that
indicate such failures. LOSS_LOCK signal will be asserted if any of the three powered up PLLs loses frequency lock for any event other than PLL
shutdown. Lock is determined by checking that the reference and feedback clocks are within 1/2 period of each other.Loss_LOCK signal may be falsely
asserted when
- Spread Spectrum is turned on for any of the PLLs
- Fractional divider is used for any of the PLLs
- the reference and feedback clocks are not within 1/2 period of each other.
LOSS_CLKIN is asserted when the currently selected clock is lost or is asserted when both clocks are lost. In the event of the selected clock being
absent up on power up, the loss of the selected clock detection circuitry will reference an internal oscillator. LOSS_LOCK and LOSS_CLKIN cannot be
used as reliable inputs to other devices.
SWITCHOVER MODES
The IDT5V9885T features redundant clock inputs which supports both Automatic and Manual switchover mode. These two modes are determined by
the configuration bits, SM (0x34). The primary clock source can be programmed, via the PRIMCLK bit, to be either XTALIN/REFIN or CLKIN, which is
determined by the PRIMCLK bit. The other clock source input will be considered as the secondary source. This is more detailed in the 'REFERENCE
CLOCK INPUT PINS AND SELECTION'. Note that the switchover modes are asynchronous. If the reference clocks are directly routed to OUTx with no
phase relationship, short pulses can be generated during switchover. The automatic switchover mode will work only when the primary clock source is
XTALIN/REFIN.
MANUAL SWITCHOVER MODE
When SM[1:0] is "0x", the redundant inputs are in manual switchover mode. In this mode, CLK_SEL pin is used to switch between the primary and
secondary clock sources. As previously mentioned, the primary and secondary clock source setting is determined by the PRIMCLK bit. During the
switchover, no glitches will occur at the output of the device, although there may be frequency and phase drift, depending on the exact phase and
frequency relationship between the primary and secondary clocks. If GOUT1 is used as LOSS_CLKIN, it indicates loss of primary clock.
AUTOMATIC SWITCHOVER MODE
When SM[1:0] is "11", the redundant inputs are in automatic revertive switchover mode.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9885TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| IDT5V9885TPFGI | 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V9885TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888NLGI | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5V9888NLGI8 | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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