I2
參數(shù)資料
型號(hào): IDT5V9885TNLGI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/39頁
文件大?。?/td> 0K
描述: IC CLOCK GEN PLL 500MHZ 28VFQFPN
標(biāo)準(zhǔn)包裝: 490
類型: *
PLL: 帶旁路
輸入: LVCMOS,LVTTL
輸出: LVCMOS,LVDS,LVPECL,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:6
差分 - 輸入:輸出: 無/是
頻率 - 最大: 500MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-VFQFPN(6x6)
包裝: 托盤
其它名稱: 800-2580
22
INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
PROGRAMMING THE DEVICE
I2C and JTAG may be used to program the 5V9885T. The I2C/JTAG pin selects the I2C when HIGH and JTAG when LOW. Note that the TRST pin needs
to be LOW for I2C mode.
Hardwired Parameters for the IDT5V9885T
JTAG identification number = 32'b0000_0000001110101100_00000110011_1
Device (slave) address = 7'b1101010
ID Byte for the 5V9885T = 8'b00010000
I2C PROGRAMMING
The 5V9885T is programmed through an I2C-Bus serial interface, and is an I2C slave device. The read and write transfer formats are supported. The first
byte of data after a write frame to the correct slave address is interpreted as the register address; this address auto-increments after each byte written or read.
The frame formats are shown below.
SDA
SCL
S
Start
Condition
Data Frame
Data is stable during
clock HIGH
Stop
Condition
P
SCL
SDA
MSB
LSB
R/W
7-bit slave address
R/W
0 - Slave will be written by master
1 - Slave will be read by master
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a "1" bit.
ACK from Slave
1
0
1
0
1
0
Figure 1: Framing
Figure 2: First Byte Transmittetd on I2C Bus
Each frame starts with a "Start Condition" and ends with an "End Condition". These are both generated by the Master device.
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