- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9194 > IDT5V9885TNLGI (IDT, Integrated Device Technology Inc)IC CLOCK GEN PLL 500MHZ 28VFQFPN PDF資料下載
參數(shù)資料
| 型號： | IDT5V9885TNLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 36/39頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-VFQFPN（6x6） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2580 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁
6
INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
Spread Spectrum
Pre-Divider (D) Values
Multiplier (M) Values
Programmable Loop Bandwidth
Generation Capability
PLL0
1 - 255
2 - 8190
yes
PLL1
1 - 255
2 - 8190
yes
PLL2
1 - 255
1 - 4095
yes
no
REFERENCE CLOCK INPUT PINS AND
SELECTION
The 5V9885T supports up to two clock inputs. One of the clock inputs
(XTALIN/ REFIN) can be driven by either an external crystal or a reference
clock. The second clock input (CLKIN) can only be driven from an external
referenceclock.Eitherclockinputcanbesetasatheprimaryclock. Theprimary
clock designation is to establish which is the main reference clock to the PLLs.
Thenon-primaryclockisdesignatedasthesecondaryclockincasetheprimary
clock goes absent and a backup is needed. The PRIMCLK bit (0x34)
determines which clock input will be the primary clock. When PRIMCLK bit is
"0",itwillselectXTALIN/REFINastheprimary,andwhen"1",itwillselectCLKIN
as the primary. The two external reference clocks can be manually selected
using the GIN5/CLK_SEL pin, except in Manual Frequency Control (MFC)
mode 2, or via programming by hard wiring the CLK_SEL pin and toggling the
PRIMCLKbit. FormoredetailsontheMFCmodes,refertotheCONFIGURING
MULTI-PURPOSE I/Os section. When CLK_SEL is LOW, the primary clock
isselectedandwhenHIGH,thesecondaryclockisselected. TheSMbits(0x34)
must be set to "0x" for manual switchover which is detailed in SWITCHOVER
MODESsection.
XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)
Crystal Input (XTALIN/REFIN)
Thecrystaloscillatorsshouldbefundamentalmodequartzcrystals:overtone
crystals are not suitable. Crystal frequency should be specified for parallel
resonance with 50maximum equivalent series resonance.
When the XTALIN/REFIN pin is driven by a crystal, it is important to set the
internal oscillator inverter drive strength and internal tuning/load capacitor
values correctly to achieve the best clock performance. These values are
programmable through either I2C or JTAG interface to allow for maximum
compatibilitywithcrystalsfromvariousmanufacturers,processes,performances,
and qualities. The internal load capacitors are true parallel-plate capacitors for
ultra-linear performance. Parallel-plate capacitors were chosen to reduce the
frequencyshiftthatoccurswhennon-linearloadcapacitanceinteractswithload,
bias, supply, and temperature changes. External non-linear crystal load
capacitors should not be used for applications that are sensitive to absolute
frequencyrequirements.Thevalueoftheinternalloadcapacitorsaredetermined
byXTALCAP[7:0]bits,(0x07).Theloadcapacitancecanbesetwitharesolution
of 0.125 pF for a total crystal load range of 3.5pF to 35.5pF. This value should
be set to two times the crystal load capacitance value stated by the vendor,
subtracting out board capacitance value. Check with the vendor's crystal load
capacitancespecificationfortheexactsettingtotunetheinternalloadcapacitor.
The following equation governs how the total internal load capacitance is set.
Ex.: For crystal capacitance = 12pF
For board capacitance = 3pF each leg
XTALCAP = 2x [12-3] = 18pF
GIN5/CLK_SEL
Selected Clock Input
L
Primary
H
Secondary
Parameter
Bits
Step
Min
Max
Units
XTALCAP
8
0.125
0
32
pF
When using an external reference clock instead of a crystal on the XTAL/
REFINpin,theinputloadcapacitorsmaybecompletelybypassed.Thisallows
for the input frequency to be up to 200MHz. When using an external reference
clock,theXTALOUTpinmustbeleftfloating,XTALCAPmustbeprogrammed
to the default value of "0", and crystal drive strength bit, XDRV (0x06), must
be set to the default value of "11".
CLKIN Pin
CLKIN pin is a regular clock input pin, and can be driven up to 400MHz.
PRE-SCALER, FEEDBACK-DIVIDER, AND
POST-DIVIDER
Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider
whichallowstheusertogeneratethreeuniquenon-integer-relatedfrequencies.
For output banks OUT2-OUT6, each bank has a 10-bit post-divider. The
following equation governs how the frequency on output banks OUT2-6 is
calculated.
FOUT = FIN * D
(Eq. 2)
Where FIN is the reference frequency, M is the total feedback-divider value,
Disthepre-scalervalue,Pisthetotalpost-dividervalue,andFOUTistheresulting
output bank frequency. The value 2 in the denominator is due to the divide-
by-2 on each of the output banks OUT2-6. Note that OUT1 does not have any
typeofpost-divider. Also,programminganyofthedividersmaycauseglitches
on the outputs.
Pre-Scaler
D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for
PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the
referenceclockwithintegervaluesrangingfrom1to255. Tomaintainlowjitter,
thedivideddownclockmustbehigherthan400KHz;itisbesttousethesmallest
D divider value possible. If D is set to '0x00', then this will power down the PLL
and all the outputs associated with that PLL.
M
P * 2
( )
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X9251TS24Z-2.7 | IC XDCP QUAD 256TAP 100K 24-SOIC |
| X9268US24IZ | IC XDCP DUAL 256TAP 50K 24-SOIC |
| X9268TS24IZ | IC XDCP DUAL 256TAP 100K 24-SOIC |
| ICS87949AYILF | IC CLK GENERATOR /1 /2 52-LQFP |
| VI-26V-MW | CONVERTER MOD DC/DC 5.8V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9885TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| IDT5V9885TPFGI | 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V9885TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888NLGI | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5V9888NLGI8 | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。