- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9194 > IDT5V9885TNLGI (IDT, Integrated Device Technology Inc)IC CLOCK GEN PLL 500MHZ 28VFQFPN PDF資料下載
參數(shù)資料
| 型號： | IDT5V9885TNLGI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 24/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL |
| 輸出： | LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 500MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-VFQFPN（6x6） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2580 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
30
INDUSTRIALTEMPERATURERANGE
IDT5V9885T
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR
AC TIMING ELECTRICAL CHARACTERISTICS
(SPREAD SPECTRUM GENERATION = OFF)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max
Unit
fIN
Input Frequency
Input Frequency Limit
1(1)
—
400
MHz
1/t1
OutputFrequency
Single Ended Clock output limit (LVTTL)
0.0049
—
200
MHz
Differential Clock output limit (LVPECL/ LVDS)
0.0049
—
500
fVCO
VCO Frequency
VCO operating Frequency Range
10
—
1200
MHz
fPFD
PFD Frequency
PFD operating Frequency Range
0.4(1)
—
400
MHz
fBW
LoopBandwidth
Based on loop filter resistor and capacitor values
0.03
—
40
MHz
t2
Input Duty Cycle
Duty Cycle for Input
40
—
60
%
t3
Output Duty Cycle
Measured at VDD/2, FOUT ≤200MHz
45
—
55
%
Measured at VDD/2, FOUT > 200MHz
40
—
60
Slew Rate
Single-Ended Output clock rise and fall time,
—
2.75
—
SLEWx(bits) = 00
20% to 80% of VDD (Output Load = 15pf)
Slew Rate
Single-Ended Output clock rise and fall time,
—
2
—
t4(2)
SLEWx(bits) = 01
20% to 80% of VDD (Output Load = 15pf)
V/ns
Slew Rate
Single-Ended Output clock rise and fall time,
—
1.25
—
SLEWx(bits) = 10
20% to 80% of VDD (Output Load = 15pf)
Slew Rate
Single-Ended Output clock rise and fall time,
—
0.75
—
SLEWx(bits) = 11
20% to 80% of VDD (Output Load = 15pf)
Rise Times
LVDS, 20% to 80%
—
850
—
t5
Fall Times
—
850
—
ps
Rise Times
LVPECL, 20% to 80%
—
500
—
Fall Times
—
500
—
t6
Outputthree-stateTiming
Time for output to enter or leave three-state mode
—
150 +
ns
after SHUTDOWN/OE switches
1/FOUTX
t7
Clock Jitter(3,7)
Peak-to-peakperiodjitter,
fPFD > 20MHz
—
150
ps
CLK outputs measured at VDD/2
fPFD < 20MHz
—
200
—
t8
Output Skew
Skew between output to output on the same bank
—
150
ps
(bank 4 and bank 5 only)(4, 5)
t9
Lock Time
PLL Lock Time from Power-up(6)
—
10
20
ms
t10
Lock time(8)
PLL Lock time from shutdown mode
—
20
100
s
NOTES:
1. Practical lower input frequency is determined by loop filter settings.
2. A slew rate of 2V/ns or greater should be selected for output frequencies of 100MHz and higher.
3. Input frequency is the same as the output with all output banks running at the same frequency.
4. Skew measured between all in-phase outputs in the same bank.
5. Skew measured between the cross points of all differential output pairs under identical input and output interfaces, transitions and load conditions on any one device.
6. Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
7. Guaranteed by design but not production tested. Actual jitter performance may vary depending on the configuration.
8. Actual PLL lock time depends on the loop configuration.
SPREAD SPECTRUM GENERATION SPECIFICATIONS
Symbol
Parameter
Description
Min.
Typ.
Max
Unit
fIN
Input Frequency
Input Frequency Limit
1(1)
—
400
MHz
fMOD
Mod Freq
ModulationFrequency
—
33
—
kHz
fSPREAD
Spread Value
Amount of Spread Value (Programmable) - Down Spread
-0.5, -1, -2.5, -3.5, -4
%fOUT
Amount of Spread Value (Programmable) - Center Spread
-2.0 to +2.0
NOTE:
1. Practical lower input frequency is determined by loop filter settings.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X9251TS24Z-2.7 | IC XDCP QUAD 256TAP 100K 24-SOIC |
| X9268US24IZ | IC XDCP DUAL 256TAP 50K 24-SOIC |
| X9268TS24IZ | IC XDCP DUAL 256TAP 100K 24-SOIC |
| ICS87949AYILF | IC CLK GENERATOR /1 /2 52-LQFP |
| VI-26V-MW | CONVERTER MOD DC/DC 5.8V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5V9885TNLGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 28VFQFPN |
| IDT5V9885TPFGI | 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| IDT5V9885TPFGI8 | 制造商:Integrated Device Technology Inc 功能描述:IC CLOCK GEN PLL 500MHZ 32TQFP |
| IDT5V9888NLGI | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5V9888NLGI8 | 功能描述:IC CLK GEN 3.3V EEPROM 28-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。