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參數(shù)資料
| 型號： | ICY7C1362C-166BGXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| 中文描述： | 512K X 18 CACHE SRAM, 3.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 25/31頁 |
| 文件大?。?/td> | 432K |
| 代理商： | ICY7C1362C-166BGXI |
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PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 25 of 31
ZZ Mode Timing
[27, 28]
Ordering Information
Speed
(MHz)
250
Ordering Code
CY7C1360C-250AXC
CY7C1362C-250AXC
CY7C1360C-250AXI
CY7C1362C-250AXI
CY7C1360C-250AJXC
CY7C1362C-250AJXC
CY7C1360C-250AJXI
CY7C1362C-250AJXI
CY7C1360C-250BGC
CY7C1362C-250BGC
CY7C1360C-250BGI
CY7C1362C-250BGI
CY7C1360C-250BZC
CY7C1362C-250BZC
CY7C1360C-250BZI
CY7C1362C-250BZI
CY7C1360C-250BGXC
CY7C1362C-250BGXC
CY7C1360C-250BGXI
CY7C1362C-250BGXI
CY7C1360C-250BZXC
CY7C1362C-250BZXC
CY7C1360C-250BZXI
CY7C1362C-250BZXI
Package
Name
A101
Part and Package Type
Operating
Range
Commercial
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
A101
Industrial
A101
Commercial
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
2 Chip Enables
Industrial
BG119
119-ball (14 x 22 x 2.4 mm)
BGA 2 Chip Enables and JTAG
Commercial
BG119
119-ball (14 x 22 x 2.4 mm)
BGA 2 Chip Enables and JTAG
Industrial
BB165D
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Commercial
BB165D
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
BG119
Lead-Free 119-ball (14 x 22 x 2.4 mm)
BGA 2 Chip Enables and
JTAG
Commercial
BG119
Lead-Free 119-ball (14 x 22 x 2.4 mm)
BGA 2 Chip Enables and
JTAG
Industrial
BB165D
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Commercial
BB165D
Lead-Free 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm)
3 Chip Enables and JTAG
Industrial
Notes:
27.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
28.DQs are in High-Z when exiting ZZ sleep mode.
Switching Waveforms
(continued)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICY7C1362C-166BZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| ICY7C1367B-166BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM |
| ICY7C1373C-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture |
| ICY7C1373D-100BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
| ICY7C1373D-100BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture |
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