參數(shù)資料
型號(hào)： ICY7C1362C-166BGXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
中文描述： 512K X 18 CACHE SRAM, 3.5 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, LEAD FREE, PLASTIC, BGA-119
文件頁(yè)數(shù)： 13/31頁(yè)
文件大?。?/td> 432K
代理商： ICY7C1362C-166BGXI
PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 13 of 31
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
CS
and t
CH
). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
相關(guān)PDF資料
PDF描述
ID100 MONOLITHIC DUAL PICO AMPERE DIODES
ID100 SCRs .5 Amp, Planar
IDT101494S7C HIGH-SPEED BiCMOS ECL STATIC RAM 64K (16K】4-BIT) SRAM
IDT100494 HIGH-SPEED BiCMOS ECL STATIC RAM 64K (16K】4-BIT) SRAM
IDT100494S10C HIGH-SPEED BiCMOS ECL STATIC RAM 64K (16K】4-BIT) SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICY7C1362C-166BZI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:9-Mbit (256K x 36/512K x 18) Pipelined SRAM
ICY7C1367B-166BGI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
ICY7C1373C-100BGI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
ICY7C1373D-100BGI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture
ICY7C1373D-100BGXI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*